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參數資料
| 型號： | TLV320DAC3120IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁數： | 47/110頁 |
| 文件大小： | 1230K |
| 代理商： | TLV320DAC3120IRHBR |
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÷N
BCLK
DAC_CLK
DAC_MOD_CLK
BDIV_CLKIN
N = 1, 2, ..., 127, 128
B0362-01
www.ti.com
SLAS659 – NOVEMBER 2009
The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel,
these clocks must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11,
bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the device
internally initiates a power-down sequence for proper shut-down. During this shutdown sequence, the
NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not take
place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 / register
37, bit D3. When both the flags indicate power-down, the MDAC divider may be powered down, followed
by the NDAC divider.
In general, all the root clock dividers should be powered down only after the child clock dividers have been
powered down for proper operation.
The TLV320DAC3120 also has options for routing some of the internal clocks to the GPIO1 output pin to
be used as general-purpose clocks in the system. The feature is shown in Figure 5-18.
Figure 5-17. BCLK Output Options
In the mode when TLV320DAC3120 is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1),
it can be driven as a divided value of BDIV_CLKIN. The division value can be programmed in page 0 /
register 30, bits D6–D0 from 1 to 128 (see Figure 5-17). The BDIV_CLKIN can itself be configured to be
one of DAC_CLK (DAC DSP clock) or DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in
page 0 / register 29, bits D1-D0. Additionally, a general-purpose clock can be driven out on GPIO1.
This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be
programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. The CDIV_CLKIN can itself be
programmed as one of the clocks among the list shown in Figure 5-18. This can be controlled by
programming the multiplexer in page 0 / register 25, bits D2–D0.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
41
Product Folder Link(s): TLV320DAC3120
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| TLV320DAC3120IRHBT | 功能描述:音頻數/模轉換器 IC Lo-Pwr Audio DAC w/ Audio Proc RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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| TLV320DAC3202 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW POWER HIGH FIDELITY I2S INPUT HEADSET IC |
| TLV320DAC3202BYZJR | 功能描述:音頻數/模轉換器 IC Lo Pwr Hi Fidelity I2S Input Headset IC RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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