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參數資料
| 型號： | TLV320DAC3120IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁數： | 65/110頁 |
| 文件大?。?/td> | 1230K |
| 代理商： | TLV320DAC3120IRHBR |
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SLAS659 – NOVEMBER 2009
www.ti.com
Page 0 / Register 31: Codec Secondary Interface Control 1
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
000: Secondary BCLK is obtained from GPIO1 pin.
001–111: Reserved.
D4–D2
R/W
000
000: Secondary WCLK is obtained from GPIO1 pin.
001–111: Reserved.
D1–D0
R/W
00
00: Secondary DIN is obtained from the GPIO1 pin.
01–11: Reserved.10: Reserved.
Page 0 / Register 32: Codec Secondary Interface Control 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
Reserved
D3
R/W
0
0: Primary BCLK is fed to codec serial-interface and ClockGen blocks.
1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks.
D2
R/W
0
0: Primary WCLK is fed to codec serial-interface block.
1: Secondary WCLK is fed to codec serial-interface block.
D1
R/W
0
Reserved
D0
R/W
0
0: Primary DIN is fed to codec serial-interface block.
1: Secondary DIN is fed to codec serial-interface block.
Page 0 / Register 33: Codec Secondary Interface Control 3
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
D6
R/W
0
0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
D5–D4
R/W
00
00: Primary WCLK output = internally generated DAC_fS
01: Reserved
10: Primary WCLK output = secondary WCLK
11: Reserved
D3–D2
R/W
00
00: Secondary WCLK output = primary WCLK
01: Secondary WCLK output = internally generated DAC_fS clock
10: Reserved
11: Reserved
D1
R/W
0
Reserved
D0
R/W
0
Reserved
Page 0 / Register 34: I2C Bus Condition
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Reserved. Write only the reset value to these bits.
D5
R/W
0
0: I2C general-call address is ignored.
1: Device accepts I2C general-call address.
D4–D0
R/W
0 0000
Reserved. Write only zeros to these bits.
Page 0 / Register 35 Through Page 0 / Register 36: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–
R
XXXX XXXX
Reserved. Write only zeros to these bits.
58
REGISTER MAP
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3120
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| TLV320DAC3202BYZJR | 功能描述:音頻數/模轉換器 IC Lo Pwr Hi Fidelity I2S Input Headset IC RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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