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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 14/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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21
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Parameter
Symbol
Conditions/Description
Min.
Typ.
Max.
Units
Lock Indicator/PECL Current Program I/O (LOCK/IPRG)
Low-level input current
IIL
PECL mode
-1
1
mA
High-level output source current
IOH
CMOS mode; V0 = 2.4V
-25
-38
mA
Low-level output sink current
IOL
CMOS mode; V0 = 0.4V
59
mA
Output impedance*
ZOH
V0 = 0.5VDD; output driving high
66
W
ZOL
V0 = 0.5VDD; output driving low
76
Short circuit source current*
ISCH
V0 = 0V; shorted for 30s, max.
-47
mA
Short circuit sink current*
ISCL
V0 = 5V; shorted for 30s, max.
47
mA
Clock Outputs, CMOS Mode (CLKN, CLKP)
High-level output source current
IOH
V0 = 2.4V
-45
-68
mA
Low-level output sink current
IOL
V0 = 0.4V
15
20
mA
Output impedance*
ZOH
V0 = 0.5VDD; output driving high
28
W
ZOL
V0 = 0.5VDD; output driving low
33
Short circuit source current *
ISCH
V0 = 0V; shorted for 30s, max.
-100
mA
Short circuit sink current*
ISCL
V0 = 5V; shorted for 30s, max.
100
mA
Clock Outputs, PECL Mode (CLKN, CLKP)
IPRG current to output current ratio
1:4
Low-level output sink current
IOH
IPRG input current = 15mA
60
mA
Tristate output current
IZ
-10
10
mA
Table 14: DC Electrical Specifications (continued)
Table 15: AC Timing Specifications
Parameter
Symbol
Conditions/Description
Min.
Typ.
Max.
Units
Overall
Output frequency*
fO(max)
CMOS outputs
130
MHz
PECL outputs
230
VCO frequency*
fVCO
Low phase jitter oscillator (OSCTYPE = 0)
VCOSPD = 0
40
160
MHz
VCOSPD = 1
40
100
FS6031 compatible oscillator (OSCTYPE = 1)
VCOSPD = 0
40
230
VCOSPD = 1
40
140
VCO gain*
AVCO
Low phase jitter oscillator (OSCTYPE = 0)
VCOSPD = 0
125
MHz/V
VCOSPD = 1
75
FS6031 compatible oscillator (OSCTYPE = 1)
VCOSPD = 0
130
VCOSPD = 1
78
Loop filter time constant*
LFTC = 0
13.5
ms
LFTC = 1
135
Rise time*
tr
CMOS Outputs, VO = 0.5V to 4.5V; CL = 15pF
1.1
ns
Fall time*
tf
CMOS Outputs, VO = 4.5V to 0.5V; CL = 15pF
0.8
ns
Lock time (main loop)*
Frequency synthesis
200
ms
Line locked modes (8kHz reference)
10
ms
Disable time
From falling edge of SCL for the last data bit
(SHUT = 1 to 0) to output locked
10
ms
Divider Modulus
Feedback divider
NF
FBKDIV[13:0] (See also Table 2)
8
16383
Reference divider
NR
REFDIV[11:0]
1
4095
Post divider
NP1
POST1[1:0] (See also Table 8)
1
8
NP2
POST2[1:0] (See also Table 8)
1
5
NP3
POST3[1:0] (See also Table 8)
1
5
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not production tested to any specific limits. Min. and Max. characterization data are ± 3
s from typical.
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not production tested to any specific limits. Min. and Max. characterization data are ± 3
s from typical.
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