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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 29/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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35
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
However, the 31.5kHz line reference signal is too low in frequency for the internal loop filter to be used. A series combination of a 0.015
mF
capacitor and a 15k
W resistor from power (VDD) to the EXTLF pin provides an external loop filter. A 100pF to 220pF capacitor in parallel with the
combination may improve the filter performance.
For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but
less than 230MHz. The VCO frequency (fVCO) can be calculated by
Px
F
HSYNC
VCO
N
f
=
Setting the post divider equal to four (NPx=4) is a reasonable solution, although there are a number of values that will work. Try to keep
5000
<
Px
F
N
to avoid divider values from becoming too large. These settings place the VCO frequency at about 100MHz.
Calculate the ideal charge pump current (Ipump) as
VCO
lf
Px
F
HSYNC
pump
A
C
R
N
kHz
f
I
2
15
=
where Rlf is the external loop filter series resistor, Clf is the external loop filter series capacitor and AVCO is the VCO gain. The VCO gain is either:
AVCO=125MHz/V if the high range is selected, or
AVCO=75MHz/V if the low range is selected.
See Table 15 for more information on the VCO range. With fhsync=31.5kHz, Clf=0.015
mF, Rlf=15kW, NF=800, NPx=4, and AVCO=125MHz/V, the charge
pump current is 39.3
mA. A 220pF cap across the entire loop filter is also helpful.
13.2 Example Programming
To generate 800 pixel clocks between HSYNC pulses occurring on the line reference signal every 31.5kHz, program the following (refer to Figure
26):
Clear the OSCTYPE bit to 0
Turn off the crystal oscillator via XLROM=7
Set the PFD inputs to select the REF pin and the feedback divider via PDREF=1 and PDFBK=0
Set the feedback divider input to select the post divider via FBKDSRC=0
Set the feedback divider (NF) to a modulus of 800 (the desired number of pixel clocks per line) via FBKDIV[14:0]
Set NP1=4, NP2=1 and NP3=1 for a combined post divider modulus of NPx=4 via POST1[1:0], POST2[1:0] and POST3[1:0].
Select the external loop filter via EXTLF=1
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector
Set VCOSPD=1 to select the VCO low speed range
Set MLCP[1:0] to 3 to select the 32
mA range
The output clock frequency fCLK is 25.175MHz, with an internal VCO frequency of 100.8MHz. Note that the crystal loop was unused in this
application.
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