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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 33/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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VCXO Frequency From Table
10 (fVCXO, MHz)
20.00
19.44
25.248
24.576
39
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
The goal is to choose the highest crystal frequency from Table 10 that generates the smallest value of NR.
The equation establishing the output frequency (fCLK) as a function of the input VCXO frequency is
R
F
VCXO
CLK
N
f
=
where NF is the feedback divider modulus.
Choose a few different crystal frequencies from Table 10 and factor both the input VCXO and output clock frequencies into prime numbers. Look
for the factors that will give the smallest modulus for NR with the largest FVCXO. The output and VCXO frequencies and the reduced factors from
Eqn. 1 are in Table 22.
Table 22: Clock Regenerator Example
VCXO
CLK
f
R
F
N
20000000
51840000
125
324
19440000
51840000
3
8
25248000
51840000
263
540
24576000
51840000
64
135
A 19.44MHz crystal provides the smallest modulus for NR (NR=3) with the highest crystal frequency.
Finally, choose a post divider (NPx) modulus that keeps the VCO frequency in its most comfortable range. The VCO frequency (fVCO) can be
calculated by
Px
CLK
VCO
N
f
=
Selecting an overall modulus of NPx=3 sets the VCO frequency at 155.52MHz when the loop is locked.
15.2 Example Programming
To generate a de-jittered output frequency of 51.84MHz from an 8kHz reference, program the following (refer to Figure 28):
Program the VCXO control ROM to 3 via XLROM[2:0] to select an external 19.44MHz crystal
Enable the VCXO fine tune via XLVTEN=1
Enable the crystal loop PFD via XLPDEN=0 and XLSWAP=0
Set the reference divider input to select the VCXO via REFDSRC
Set the PFD input to select the reference divider and the feedback divider via PDREF and PDFBK
Set the reference divider (NR) to a modulus of 3 via REFDIV[11:0]
Set the feedback divider input to select the VCO via FBKDSRC
Set the feedback divider (NF) to a modulus of 8 via FBKDIV[14:0]
Set NP1=1, NP2=3 and NP3=1 for a combined post divider modulus of NPx=3 via POST1[1:0], POST2[1:0] and POST3[1:0].
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