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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 37/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and stability.
The loop gain of a PLL is the product of all of the gains within the loop.
Establish the basic operating parameters:
6
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
4.2.2 Phase Alignment
To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The source for the
feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider must be dividing at a
multiple of the post divider.
Phase
Frequency
Detect
Feedback
Divider (N
F)
VCO
f
IN
f
OUT
Reference
Divider (N
R)
Post
Divider (N
F)
f
IN
f
OUT
Figure 7: Aligned I/O Phase
4.2.3 Phase Sampling and Initial Alignment
However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the initial
synchronization of the output phase to input phase, a phase align "flag" makes a transition (zero to one or one to zero) when the output clock
phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input clock phase.
First, the FS6131 is used to sample the output clock with the feedback source clock and set/clear the phase align flag when the two clocks match
to within a feedback source clock period. Then, the clock gobbler is used to delay the output phase relative to the input phase one VCO clock at
a time until a transition on the flag occurs. When a transition occurs, the output and input clocks are phase aligned.
To enter this mode, set STAT[1] to one and clear STAT[0] to zero. If the CMOS bit is set to one, the LOCK/IPRG pin can display the flag. The flag
is always available under software control by reading back the STAT[1] bit, which will be overwritten by the flag in this mode.
4.2.4 Feedback Divider Monitoring
The feedback divider clock can be brought out the LOCK/IPRG pin independent of the output clock to allow monitoring of the feedback divider
clock. To enter this mode, set both the STAT[1] and STAT[0] bits to one. The CMOS bit must also be set to one to enable the LOCK/IPRG pin as
an output.
4.3 Loop Gain Analysis
Set the charge pump current:
Set the loop filter values:
Set the VCO gain (VCOSPD):
Set the feedback divider:
Set the reference frequency (at
the input to the phase detector):
A
I
chgpump
m
10
=
pF
C
F
C
k
R
LF
220
015
.
0
15
2
1
=
W
=
m
kHz
f
REF
20
=
3500
=
F
N
V
MHz
A
VCO
/
230
=
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