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參數(shù)資料
| 型號(hào)： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁(yè)數(shù)： | 39/40頁(yè) |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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8
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
The loop phase angle is:
[]
)
2
(
arg
i
LOOP
i
f
j
K
p
=
Q
-150°
Frequency (f
i)
-100°
P
h
a
s
e
0.1kHz
1kHz
10kHz
100kHz
Figure 9: Loop Phase vs. Frequency
A Nyquist plot of gain vs. amplitude is shown below.
45°
0°
315°
270°
225°
180°
135°
90°
0.2
0.4
0.6
0.8
1.0
Phase
Amplitude
1.2
Gain Margin
Phase
Margin
Figure 10: Loop Nyquist Plot
4.4 Voltage-Controlled Crystal Oscillator
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6131 system components. Loading capacitance for the crystal
is internal to the device. No external components (other than the resonator itself) are required for operation of the VCXO.
The resonator loading capacitance is adjustable under register control. This feature permits factory coarse tuning of inexpensive resonators to the
necessary precision for digital video applications. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the
XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is 1.5pF nominal, and the effect is shown in
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