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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 7/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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15
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
6.0 Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT[1] (Bit 63).
Table 3: Register Map
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 7
STAT[1]
(Bit 63)
STAT[0]
(Bit 62)
XLVTEN
(Bit 61)
CMOS
(Bit 60)
XCT[3]
(Bit 59)
XCT[2]
(Bit 58)
XCT[1]
(Bit 57)
XCT[0]
(Bit 56)
00 = Crystal Loop - Lock Status
0 = Fine Tune
Inactive
0 = PECL
VCXO Coarse Tune
See Table 11
01 = Crystal Loop - Out of Range
10 = Main Loop - Phase Status
1 = Fine Tune
Active
1 = CMOS
Lock Status
11 = Feedback Divider Output
Byte 6
XLPDEN
(Bit 55)
XLSWAP
(Bit 54)
XLCP[1]
(Bit 53)
XLCP[0]
(Bit 52)
XLROM[2]
(Bit 51)
XLROM[1]
(Bit 50)
XLROM[0]
(Bit 49)
GBL
(Bit 48)
0 = Crystal Loop
Operates
0 = Use with
External VCXO
00 = 1.5
mA
Crystal Loop Control
See Table 10
0 = No Clock
Phase Adjust
01 = 5
mA
1 = Crystal Loop
Powered Down
1 = Use with
Internal VCXO
10 = 8
mA
1 = Clock Phase
Delay
11 = 24
mA
Byte 5
OUTMUX[1]
(Bit 47)
OUTMUX[0]
(Bit 46)
OSCTYPE
(Bit 45)
VCOSPD
(Bit 44)
LFTC
(Bit 43)
EXTLF
(Bit 42)
MLCP[1]
(Bit 41)
MLCP[0]
(Bit 40)
00 - VCO Output
0 = Low Phase
Jitter Oscillator
0 = High Speed
Range
0 = Short Time
Constant
0 = Internal Loop
Filter
00 = 1.5
mA
01 = Reference Divider Output
01 = 5
mA
10 = Phase Detector Input
1 = FS6031
Oscillator
1 = Low Speed
Range
1 = Long Time
Constant
1 = External Loop
Filter
10 = 8
mA
11 = VCXO Output
11 = 24
mA
Byte 4
FBKDSRC[1]
(Bit 39)
FBKDSRC[0]
(Bit 38)
FBKDIV[13]
(Bit 37)
FBKDIV[12]
(Bit 36)
FBKDIV[11]
(Bit 35)
FBKDIV[10]
(Bit 34)
FBKDIV[9]
(Bit 33)
FBKDIV[8]
(Bit 32)
00 = Post Divider Output
8192
4096
2048
1024
512
256
01 = FBK Pin
10 = Post Divider Input
M Counter
11 = FBK Pin
Byte 3
FBKDIV[7]
(Bit 31)
FBKDIV[6]
(Bit 30)
FBKDIV[5]
(Bit 29)
FBKDIV[4]
(Bit 28)
FBKDIV[3]
(Bit 27)
FBKDIV[2]
(Bit 26)
FBKDIV[1]
(Bit 25)
FBKDIV[0]
(Bit 24)
128
64
32
16
8
4
2
1
M-Counter
A Counter - See Table 2
Byte 2
Reserved (0)
POST3[1]
(Bit 21)
POST3[1]
(Bit 20)
POST2[1]
(Bit 19)
POST2[0]
(Bit 18)
POST1[1]
(Bit 17)
POST1[0]
(Bit 16)
00 = Divide by 1
01 = Divide by 3
01 = Divide by 2
10 = Divide by 5
10 = Divide by 4
11 = Divide by 4
11 = Divide by 8
Byte 1
PDFBK
(Bit 15)
PDREF
(Bit 14)
SHUT
(Bit 13)
REFDSRC
(Bit 12)
REFDIV[11]
(Bit 11)
REFDIV[10]
(Bit 10)
REFDIV[9]
(Bit 9)
REFDIV[8]
(Bit 8)
0 = Feedback Divider
0 = Reference Divider
0 = Main Loop
Operates
0 = VXCO
2048
1024
512
256
1 = FBK Pin
1 = REF Pin
1 = Main Loop
Powered Down
1 = REF Pin
Byte 0
REFDIV[7]
(Bit 7)
REFDIV[6]
(Bit 6)
REFDIV[5]
(Bit 5)
REFDIV[4]
(Bit 4)
REFDIV[3]
(Bit 3)
REFDIV[2]
(Bit 2)
REFDIV[1]
(Bit 1)
REFDIV[0]
(Bit 0)
128
64
32
16
8
4
2
1
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