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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 27/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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33
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Deciding how to apportion the denominator integers between the reference divider and the post divider is an iterative process. To obtain the best
performance, the VCO should be operated at the highest frequency possible without exceeding its upper limit of 230MHz. (see Table 15). The
VCO frequency (fVCO) can be calculated by
R
F
REF
VCO
N
f
=
Recall that the reference divider can have a value between 1 and 4096, but the post divider is limited to values derived from
3
2
1
P
Px
N
=
where the values NP1, NP2 and NP3 are found in Table 8.
In this example, the smallest integer that can be removed from the denominator of Eqn. 2 is three. Set the post divider at NPx=3, and the ratio of
fCLK to fREF becomes (from Eqn. 1)
()
3
1
7
3
11
5
2
1
3
=
REF
CLK
f
Unfortunately, a post divider modulus of three requires a VCO frequency of 300MHz, which is greater than the allowable fVCO noted in Table 15.
For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but
less then 230MHz. Therefore, the reference divider cannot be reduced below the modulus of 327 (or 63) as shown in Eqn. 2.
However, the VCO can still be operated at a frequency higher than fCLK. Multiplying both the numerator and the denominator by two does not alter
the output frequency, but it does increase the VCO frequency.
()
2
1
63
880
2
1
7
3
2
11
5
2
1
2
1
3
=
=
=
Px
R
F
REF
CLK
N
f
As Eqn. 3 shows, the VCO frequency can be doubled by multiplying the feedback divider by two. Set the post divider to two to return the output
frequency to the desired modulus. These divider settings place the VCO frequency at 200MHz.
12.2 Example Programming
To generate 100.000MHz from 14.318MHz, program the following (refer to Figure 25):
Set the reference divider input to select the VCXO via REFDSRC=0
Set the PFD input to select the reference divider and the feedback divider via PDREF=0 and PDFBK=0
Set the reference divider (NR) to a modulus of 63 via REFDIV[11:0]
Set the feedback divider input to select the VCO via FBKDSRC=1
Set the feedback divider (NF) to a modulus of 880 via FBKDIV[14:0]
Set NP1=2, NP2=1 and NP3=1 for a combined post divider modulus of NPx=2 via POST1[1:0], POST2[1:0] and POST3[1:0].
Select the internal loop filter via EXTLF=0
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector
Set VCOSPD=0 to select the VCO high speed range
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