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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 36/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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5
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety
of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
÷÷
è
÷÷
è
=
Px
R
F
REF
CLK
N
f
1
The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be
achieved exactly.
Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.
4.2 Phase Adjust and Sampling
In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock. Since the
VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input clock. Every cycle of
the input clock equals NR/NF cycles of the VCO clock.
Phase
Frequency
Detect
Feedback
Divider (N
F)
VCO
f
IN
f
OUT
Reference
Divider (N
R)
f
IN
f
OUT
Figure 5: Simple PLL
The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because the post
divider is outside the feedback loop.
Phase
Frequency
Detect
Feedback
Divider (N
F)
VCO
f
IN
f
OUT
Reference
Divider (N
R)
f
IN
f
VCO
Post
Divider (N
F)
f
VCO
f
OUT
?
Figure 6: PLL with Post Divider
4.2.1 Clock Gobbler (Phase Adjust)
The clock gobbler circuit takes advantage of the unknown relationship between input and output clocks to permit the adjustment of the
CLKP/CLKN output clock phase relative to the REF input. The clock gobbler circuit removes a VCO clock pulse before the pulse clocks the post
divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase.
To adjust the phase relationship, switch the feedback divider source to the post divider input via the FBKDSRC bit, and toggle the GBL register
bit. The clock gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one.
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