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參數(shù)資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 746K |
| 代理商： | 11274-502-XTD |
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32
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
12.1 Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
Suppose that the reference source frequency is 14.318MHz and the desired output frequency is 100MHz.
First, factor the 14.318MHz reference frequency (which is four times the NTSC television color sub-carrier) into prime numbers. The exact
expression is
11
7
5
3
2
81
.
14318181
1
7
2
5
=
REF
f
FS6131
VCXO
Divider
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Internal
Loop
Filter
EXTLF
I2C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0]
POST2[1:0]
POST1[1:0]
REFDIV[11:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF)
(f
VCO)
LOCK/
IPRG
Post
Divider
(N
Px)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
Feedback
Divider (N
F)
FBKDIV[14:0]
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK)
CLKP
R
LF
C
LF
R
IPRG
C
LP
Figure 25: Block Diagram: Stand-Alone Clock Generation
Next, express the output and input frequencies as a ratio of fCLK to fREF, where fCLK has also been converted to a product of prime numbers.
()
÷
è
=
11
7
5
3
2
5
2
81
.
14318181
00
.
100000000
1
7
2
5
8
REF
CLK
f
Simplifying the above equation yields
()
7
3
11
5
2
1
3
=
REF
CLK
f
(Eqn. 2)
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