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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 24/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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30
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
11.1.1 Example Calculation
In PECL mode, the output driver does not source current, so the VIH value is determined by the ratios of the terminating resistors using the
equation
2
1
p
CC
NMH
R
V
+
=
where Rp1 is the pull-up resistor, Rp2 is the pull-down resistor and VNMH is the desired noise margin, and
NMH
CC
IH
V
-
=
The resistor ratio must also match the line impedance via the equation
2
1
2
1
p
L
R
z
+
=
where zL is the line impedance.
Combining these equations, and solving for Rp1 gives
÷÷
è
-
+
=
NMH
CC
NMH
L
p
V
z
R
1
If the load's VIH(min) = VCC - 0.6, choose a VNMH = 0.45V. If the line impedance is 75
W, then Rp1 is about 82W. Substituting into the equation for line
impedance and solving for Rp2 gives a value of 880
W (choose 910W).
To solve for the load's VIL, an output sink current must be programmed via the IPRG pin. If the desired VIH = VCC - 1.6, choose VCC - 2.0 for some
extra margin. A sink current of 25mA through the 82
W resistor generates a 2.05V drop. The sink current is programmed via the IPRG pin, where
the ratio of IPRG current to output sink current is 1:4. An IPRG programming resistor of 750
W at VDD = 5V generates 6.6mA, or about 27mA output
sink current.
11.2 CMOS Output Mode
If a CMOS interface is desired, a transmission line is typically terminated using a series termination. Series termination adds no dc loading to the
driver, and requires less power than other resistive termination methods. In addition, no extra impedance exists from the signal line to a reference
voltage, such as ground.
R
S
z
L
z
O
DRIVER
RECEIVE
LINE
Figure 23: Series Termincation (CMOS)
As shown in Figure 23, the sum of the driver's output impedance (zO) and the series termination resistance (RS) must equal the line impedance
(zL). That is,
O
L
S
z
R
-
=
When the source impedance (zO+RS) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half of the full
signal amplitude.
2
)
(
)
(
V
z
R
z
R
z
V
L
S
O
S
O
i
=
+
=
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