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參數資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數： | 22/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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29
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 21: Sample Text Output
AMI - FS6131 Solution Text File
Line-Locked / Genlock Mode
Desired Multiple =
800
Source =
.0315MHz Reference Pin
External Loop Filter C1 = 47pF
R = 4700Ohms
Crystal Oscillator Voltage Tune Disabled
Output Stage = CMOS
Reference Divider
=
1
Feedback Divider
=
800
Post Divider
=
4
Charge Pump (uA)
=
0
EXTLF
=
1
XLVTEN
=
0
XCT
=
7
CMOS
=
1
Register 0
= 1H (1)
Register 1
= 40H (64)
Register 2
= 2H (2)
Register 3
= 20H (32)
Register 4
= 3H (3)
Register 5
= 24H (36)
Register 6
= 0H (0)
Register 7
= 17H (23)
11.0 Applications Information
11.1 PECL Output Mode
A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several undesirable effects
in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the board. Using a properly designed
series termination on each high-speed line can alleviate these problems by eliminating signal reflections.
If a PECL interface is desired, the transmission line must be terminated using a Thévenin, or dual, termination. The output stage can only sink
current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. Source current is provided by
the pull-up resistor that is part of the Thévenin termination.
R
p1
IPRG
CLKN
CLKP
{
from
PLL
R
n1
R
p2
R
n2
R
i
LOAD
z
L
z
L
z
O
PECL Mode Output
V
CC
V
CC
Figure 22: Thévenin termination (PECL)
Thévenin termination uses two resistors per transmission line. The parallel resistance of the termination resistors should be sized to equal the
transmission line impedance, taking into account the driver sink current, the desired rise and fall times, and the VIH and VIL specifications of the
load.
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