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參數資料
| 型號： | AD9910 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | 1 GSPS的，14位，3.3伏的CMOS直接數字頻率合成 |
| 文件頁數： | 22/60頁 |
| 文件大?。?/td> | 764K |
| 代理商： | AD9910 |
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AD9910
FUNCTIONAL BLOCK DETAIL
DDS CORE
The direct digital synthesizer (DDS) block generates a reference
signal (sine or cosine based on the selected DDS sine output
bit). The parameters of the reference signal (frequency, phase,
and amplitude) are applied to the DDS at its frequency, phase
offset, and amplitude control inputs, as shown in Figure 27.
Rev. 0 | Page 22 of 60
0
DDS_CLK
32
19
FREQUENCY
CONTROL
ANGLE
TO
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
PHASE
OFFSET
CONTROL
TO DAC
(MSBs)
D Q
R
ACCUMULATOR
RESET
32
16
MSB ALIGNED
AMPLITUDE
CONTROL
14
DDS SIGNAL CONTROL PARAMETERS
16
14
19
32
32
14
14
32-BIT
ACCUMULATOR
Figure 27. DDS Block Diagram
The output frequency (f
OUT
) of the AD9910 is controlled by the
frequency tuning word (FTW) at the frequency control input to
the DDS. The relationship between f
OUT
, FTW, and f
SYSCLK
is
given by
SYSCLK
OUT
f
FTW
32
2
f
=
(1)
where
FTW
is a 32-bit integer ranging in value from 0 to
2,147,483,647 (2
31
1), which represents the lower half of the
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, f
SYSCLK
).
The FTW required to generate a desired value of f
OUT
is found
by solving Equation 1 for FTW as given in Equation 2
=
SYSCLK
OUT
f
f
round
FTW
32
2
(2)
where the
round(x)
function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value. For example, for f
OUT
=
41 MHz and f
SYSCLK
= 122.88 MHz, then FTW = 1,433,053,867
(0x556AAAAB).
Programming an FTW greater than 2
31
produces an aliased
image that appears at a frequency given by
SYSCLK
OUT
f
FTW
32
2
f
1
=
(for FTW ≥ 2
31
)
The relative phase of the DDS signal can be digitally controlled
by means of a 16-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by
=
16
16
2
360
2
POW
2
Δ
POW
π
θ
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the
POW value necessary to develop an arbitrary Δθ, solve the
above equation for POW and round the result (in a manner
similar to that described for finding an arbitrary FTW in the
previous paragraphs).
The relative amplitude of the DDS signal can be digitally scaled
(relative to full scale) by means of a 14-bit amplitude scale
factor (ASF). The amplitude scale value is applied at the output
of the angle-to-amplitude conversion block internal to the DDS
core. The amplitude scale is given by
=
14
14
2
log
20
2
ASF
ASF
Scale
Amplitude
(3)
where the upper quantity is amplitude expressed as a fraction of
full scale and the lower quantity is expressed in decibels relative
to full scale. To find the ASF value necessary for a particular
scale factor, solve Equation 3 for ASF and round the result (in a
manner similar to that described for finding an arbitrary FTW
in the previous paragraphs).
When the AD9910 is programmed to modulate any of the DDS
signal control parameters, the maximum modulation sample
rate is f
SYSCLK
. This means that the modulation signal exhibits
images about multiples of f
SYSCLK
. The impact of these images
must be considered when using the device as a modulator.
14-BIT DAC OUTPUT
The AD9910 incorporates an integrated 14-bit, current output
DAC. The output current is delivered as a balanced signal using
two outputs. The use of balanced outputs reduces the potential
amount of common-mode noise present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. An
external resistor (R
SET
) connected between the DAC_RSET pin
and AGND establishes the reference current. The full-scale
output current of the DAC (I
OUT
) is produced as a scaled version
of the reference current (see the Auxiliary DAC section). The
recommended value of R
SET
is 10 kΩ.
Attention should be paid to the load termination to keep the output
voltage within the specified compliance range; voltages developed
beyond this range cause excessive distortion and can damage the
DAC output circuitry.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9910_07 | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| AD9910BSVZ | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| AD9910BSVZ-REEL | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| AD9912 | 1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| AD9913 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9910/PCBZ | 功能描述:數據轉換 IC 開發工具 1GSPS 14 bit DDS w/ parallel input port RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9910_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| AD9910BSVZ | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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