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參數(shù)資料
型號(hào)： AD9910
廠商： Analog Devices, Inc.
元件分類： XO, clock
英文描述： 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
中文描述： 1 GSPS的，14位，3.3伏的CMOS直接數(shù)字頻率合成
文件頁(yè)數(shù)： 45/60頁(yè)
文件大小： 764K
代理商： AD9910
AD9910
are synchronized). This concept is shown in Figure 52, in which
three AD9910s are synchronized with one device operating as a
master timing unit and the others as slave units.
Rev. 0 | Page 45 of 60
The master device must have its SYNC_IN pins included as part
of the synchronization distribution and delay equalization mecha-
nism in order for it to be synchronized with the slave units.
The synchronization mechanism begins with the clock
distribution and delay equalization block, which is used to
ensure that all devices receive an edge aligned REFCLK signal.
However, even though the REFCLK signal is edge aligned
among all devices, this alone does not guarantee that the clock
state of each internal clock generator is coordinated with the
others. This is the role of the Synchronization and Delay
Equalization block. This block accepts the SYNC_OUT signal
generated by the master device and redistributes it to the
SYNC_IN input of the slave units (as well as feeding it back to
the master). The goal of the redistributed SYNC_OUT signal
from the master device is to deliver an edge aligned SYNC_IN
signal to all of the sync receivers.
Assuming that all devices share the same REFCLK edge (due to
the clock distribution and delay equalization block), and all
devices share the same SYNC_IN edge (due to the synchroni-
zation and delay equalization block), then all devices should
generate an internal sync pulse in unison (assuming they all
have the same sync receiver delay value). With the further
stipulation that all devices have the same sync state preset value,
then the synchronized sync pulses cause all of the devices to
assume the same predefined clock state simultaneously. That is,
the internal clocks of all devices become fully synchronized.
The synchronization mechanism depends on the reliable gen-
eration of a sync pulse by the edge detection block in the sync
receiver. Generation of a valid sync pulse, however, requires
proper sampling of the rising edge of the delayed sync-in signal
with the rising edge of the local SYSCLK. If the edge timing of
these signals fails to meet the setup or hold time requirements
of the internal latches in the edge detection circuitry, then the
proper generation of the sync pulse is in jeopardy. The setup
and hold validation block (see Figure 53) gives the user a means
to validate that proper edge timing exists between the two
signals.
The setup and hold validation block can be disabled via the
sync timing validation disable bit in Control Function Register 2.
The validation block makes use of a user-specified time window
(programmable in increments of ~150 ps via the 4-bit sync
validation delay word in the multichip sync register). The setup
validation and hold validation circuits use latches identical to
those in the rising edge detector and strobe generator. The
programmable time window is used to skew the timing between
the rising edges of the local SYSCLK signal and the rising edges
of the delayed sync-in signal. If either the hold or setup
validation circuits fail to detect a valid edge sample, the
condition is indicated externally via the SYNC_SMP_ERR pin
(active high).
The user must choose a sync validation delay value that is a
reasonable fraction of the SYSCLK period. For example, if the
SYSCLK frequency is 1 GHz (1 ns period), then a reasonable
value is 1 or 2 (150 ps or 300 ps). Choosing too large a value can
cause the SYNC_SMP_ERR pin to generate false error signals.
Choosing too small a value may cause instability.
SYNC
PULSE
SYSCLK
DELAY
DELAY
C
4
SYNC VALIDATION
DELAY
4
4
SYNC_SMP_ERR
SYNC RECEIVER
12
SYNC TIMING VALIDATION DISABLE
SETUP
VALIDATION
HOLD
VALIDATION
D Q
SETUP AND HOLD VALIDATION
TO
CLOCK
GENERATION
LOGIC
FROM
SYNC
RECEIVER
DELAY
LOGIC
D Q
D Q
RISING EDGE
DETECTOR
AND STROBE
GENERATOR
0
Figure 53. Sync Timing Validation Block
相關(guān)PDF資料
PDF描述
AD9910_07 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
AD9910BSVZ 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
AD9910BSVZ-REEL 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
AD9912 1 GSPS Direct Digital Synthesizer w/ 14-bit DAC
AD9913 Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9910/PCBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 1GSPS 14 bit DDS w/ parallel input port RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
AD9910_07 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
AD9910BSVZ 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9910BSVZ 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100
AD9910BSVZ-REEL 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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