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參數資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 11/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
11 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
7.
Functional description
7.1 PLL clock multiplier
A 6 to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This
allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external
components are required for the operation of the PLL.
7.2 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream
using a 4
×
over-sampling principle. It is able to track jitter and frequency drift as
specified by the USB Specification Rev. 1.1
7.3 Analog transceivers
Three sets of transceiver are embedded in the chip: two are used for downstream
ports with USB connector type A; one is used for upstream port with USB connector
type B.The integrated transceivers are compliant with the Universal Serial Bus
Specification Rev 1.1 They interface directly with the USB connectors and cables
through external termination resistors.
7.4 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel/serial conversion, bit (de)stuffing, CRC
checking/generation, Packet IDentifier (PID) verification/generation, address
recognition, handshake evaluation/generation. There are separate SIE in both the HC
and the DC.
7.5 SoftConnect (in DC)
The connection to the USB is accomplished by bringing D
+
(for high-speed USB
devices) HIGH through a 1.5 k
pull-up resistor. In the ISP1161 the 1.5 k
pull-up
resistor is integrated on-chip and is not connected to V
CC
by default. The connection
is established through a command sent by the external/system microcontroller. This
allows the system microcontroller to complete its initialization sequence before
deciding to establish connection with the USB. Re-initialization of the USB connection
can also be performed without disconnecting the cable.
The ISP1161 DC will check for USB V
BUS
availability before the connection can be
established. V
BUS
sensing is provided through pin D_VBUS.
Remark:
Note that the tolerance of the internal resistors is 25%. This is higher than
the 5% tolerance specified by the USB specification. However, the overall V
SE
voltage
specification for the connection can still be met with a good margin. The decision to
make use of this feature lies with the USB equipment designer.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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