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參數資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 36/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
36 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
Control Transaction Limitations
The different phases of a Control transfer (SETUP, Data and Status) should never be
put in the same ATL.
9.6 Microprocessor loading
The maximum amount of data that can be transferred for an endpoint during one
frame is 1023 bytes. The number of USB packets that are needed for this batch of
data depends on the Maximum Packet Size that is specified.
The HC Driver has to schedule the transactions in a frame. On the other hand, the
microprocessor must have the ability to handle the interrupts coming from HC every
1 ms. It must also be able to do the scheduling for the next frame, reading the frame
information from and writing the next frame information to the buffer RAM in the time
between the end of the current frame and the start of the next frame.
9.7 Internal 15 k
pull-down resistors for downstream ports
There are four internal 15 k
pull-down resistors built in ISP1161 for the two
downstream ports: two resistors for each port. These resistors are software
selectable by programming bit 12 of the HcHardwareConfiguration register (20H -
Read, A0H - Write). When bit 12 is cleared to logic 0, it means that external 15 k
pull-down resistors should be used. Bit 12 is set to logic 1 that indicates the internal
built in 15 k
pull-down resistors will be used instead of external ones. See
Figure 33
.
This feature is a cost-saving option. However, the power on reset default value is
logic 0. If you want to use the internal resistors, the HC Driver must check this bit
status after every reset, because a reset action will clear this bit regardless of it being
a hardware reset or a software reset.
Fig 32. HC time domain behavior: example 3.
MGT956
(frame N)
(frame N
+
1)
(frame N
+
2)
(frame N
+
3)
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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