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參數資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 73/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
73 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
Table 43: HcRhPortStatus[1:2] Register: bit description
Bit
Symbol
Description
31 to 21
-
reserved
20
PRSC
PortResetStatusChange:
This bit is set at the end of the 10 ms
port reset signal. The HCD writes a logic 1 to clear this bit. Writing
a logic 0 has no effect.
0 —
port reset is not complete
1 —
port reset is complete
19
OCIC
PortOverCurrentIndicatorChange:
This bit is valid only if
overcurrent conditions are reported on a per-port basis. This bit is
set when Root Hub changes the PortOverCurrentIndicator bit. The
HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect.
0 —
no change in PortOverCurrentIndicator
1 —
PortOverCurrentIndicator has changed
18
PSSC
PortSuspendStatusChange:
This bit is set when the full resume
sequence has been completed. This sequence includes the 20 s
resume pulse, LS EOP, and 3 ms re-synchronization delay. The
HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect.
This bit is also cleared when ResetStatusChange is set.
0 —
resume is not completed
1 —
resume is completed
17
PESC
PortEnableStatusChange:
This bit is set when hardware events
cause the PortEnableStatus bit to be cleared. Changes from HCD
writes do not set this bit. The HCD writes a logic 1 to clear this bit.
Writing a logic 0 has no effect.
0 —
no change in PortEnableStatus
1 —
change in PortEnableStatus
16
CSC
ConnectStatusChange:
This bit is set whenever a connect or
disconnect event occurs. The HCD writes a logic 1 to clear this bit.
Writing a logic 0 has no effect. If CurrentConnectStatus is cleared
when a SetPortReset, SetPortEnable, or SetPortSuspend write
occurs, this bit is set to force the driver to re-evaluate the
connection status since these writes should not occur if the port is
disconnected.
0 —
no change in CurrentConnectStatus
1 —
change in CurrentConnectStatus
Remark:
If the DeviceRemovable[NDP] bit is set, this bit is set only
after a Root Hub reset to inform the system that the device is
attached.
15 to 10
-
reserved
9
LSDA
(read)
LowSpeedDeviceAttached:
This bit indicates the speed of
the device attached to this port. When set, a low-speed device is
attached to this port. When clear, a full-speed device is attached to
this port. This field is valid only when the CurrentConnectStatus is
set.
0 —
full-speed device attached
1 —
low-speed device attached
(write)
ClearPortPower:
The HCD clears the PortPowerStatus bit
by writing a logic 1 to this bit. Writing a logic 0 has no effect.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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