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參數資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 91/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
91 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
[1]
Unchanged by a bus reset.
14.1.4
Write/Read Hardware Configuration
This command is used to access the Hardware Configuration Register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
Table 81
. A bus reset will not change any
of the programmed bit values.
The Hardware Configuration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB —
write/read Hardware Configuration Register
Transaction —
write/read 1 word
Table 79: Mode Register: bit allocation
Bit
7
Symbol
DMAWD
Reset
0
[1]
Access
R/W
6
5
4
3
2
1
0
reserved
0
R/W
GOSUSP
0
R/W
reserved
0
R/W
INTENA
0
[1]
R/W
DBGMOD
0
[1]
R/W
reserved
0
[1]
R/W
SOFTCT
0
[1]
R/W
Table 80: Mode Register: bit description
Bit
Symbol
7
DMAWD
Description
A logic 1 selects 16-bit DMA bus width (bus configuration modes
0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value:
unchanged.
reserved
Writing a logic 1 followed by a logic 0 will activate ‘suspend’
mode.
reserved
A logic 1 enables all interrupts. Bus reset value: unchanged.
A logic 1 enables debug mode. where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
reserved
A logic 1 enables SoftConnect (see
Section 7.5
). This bit is
ignored if EXTPUL = 1 in the Hardware Configuration Register
(see
Table 81
). Bus reset value: unchanged.
6
5
-
GOSUSP
4
3
2
-
INTENA
DBGMOD
1
0
-
SOFTCT
Table 81: Hardware Configuration Register: bit allocation
Bit
15
Symbol
reserved
EXTPUL
Reset
0
Access
R/W
14
13
12
11
10
9
8
NOLAZY
1
R/W
CLKRUN
0
R/W
CKDIV[3:0]
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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