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參數(shù)資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 29/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
29 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
The data transfer can be done via PIO mode or DMA mode. The data transfer rate
can go up to 15 Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes
are supported. For the multi-cycle burst mode, 1, 4, or 8 cycles per burst is supported
for ISP1161.
9.4.2
Data organization
PTD data is used for every data transfer between a microprocessor and the USB bus,
and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the
payload data is placed just after the PTD, after which the next PTD is placed. For an
IN transfer, some RAM space is reserved for receiving a number of bytes that is equal
to the total bytes of the transfer. After this, the next PTD and its payload data are
placed (see
Figure 27
).
Remark:
The PTD is defined for both ATL and ITL type data transfer. For ITL, the
PTD data should be put into ITL buffer RAM, the ISP1161 takes care of the
Ping-Pong action for the ITL buffer RAM access.
The PTD data (PTD header and its payload data) is a structure of DWORD (double-
word or 4-byte) alignment. This means that the memory address is organized in steps
of 4 bytes. Therefore, the first byte of every PTD and the first byte of every payload
data are located at an address which is a multiple of 4.
Figure 28
illustrates an
example in which the first payload data is 14 bytes long, meaning that the last byte of
the payload data is at the location 15H. The next addresses (16H and 17H) are not
multiples of 4. Therefore, the first byte of the next PTD will be located at the next
multiple-of-four address, 18H.
Fig 27. Buffer RAM data organization.
MGT952
PTD of OUT transfer
RAM buffer
payload data of OUT transfer
PTD of IN transfer
empty space for IN total data
PTD of OUT transfer
payload data of OUT transfer
top
bottom
000H
7FFH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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