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參數資料
型號： ISP1161BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數： 94/127頁
文件大小： 2762K
代理商： ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
94 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
14.1.6
Write/Read DMA Configuration
This command defines the DMA configuration of ISP1161’s DC and enables/disables
DMA transfers. The command accesses the DMA Configuration Register, which
consists of 2 bytes. The bit allocation is given in
Table 85
. A bus reset will clear bit
DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 —
write/read DMA Configuration
Transaction —
write/read 1 word
[1]
Unchanged by a bus reset.
For selecting an endpoint for device DMA transfer, see
Section 11.2
.
Table 85: DMA Configuration Register: bit allocation
Bit
15
Symbol
CNTREN
Reset
0
[1]
Access
R/W
Bit
7
Symbol
Reset
0
[1]
Access
R/W
14
13
12
11
10
9
8
SHORTP
0
[1]
R/W
6
reserved
0
[1]
R/W
5
reserved
0
[1]
R/W
4
reserved
0
[1]
R/W
3
DMAEN
0
R/W
reserved
0
[1]
R/W
2
reserved
0
R/W
reserved
0
[1]
R/W
1
reserved
0
[1]
R/W
0
EPDIX[3:0]
0
[1]
R/W
BURSTL[1:0]
0
[1]
R/W
0
[1]
R/W
0
[1]
R/W
0
[1]
R/W
Table 86: DMA Configuration Register: bit description
Bit
Symbol
15
CNTREN
Description
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value:
unchanged.
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) this bit should be
cleared. Bus reset value: unchanged.
reserved
Indicates the destination endpoint for DMA, see
Table 10
.
Writing a logic 1 enables DMA transfer, a logic 0 forces the end
of an ongoing DMA transfer and generates an EOT interrupt.
Reading this bit indicates whether DMA is enabled (0 = DMA
stopped, 1 = DMA enabled). This bit is cleared by a bus reset.
reserved
Selects the DMA burst length:
00 —
single-cycle mode (1 byte)
01 —
burst mode (4 bytes)
10 —
burst mode (8 bytes)
11 —
burst mode (16 bytes).
Bus reset value: unchanged.
14
SHORTP
13 to 8
7 to 4
3
-
EPDIX[3:0]
DMAEN
2
1 to 0
-
BURSTL[1:0]
相關PDF資料
PDF描述
ISP1161BM Full-speed Universal Serial Bus single-chip host and device controller
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相關代理商/技術參數
參數描述
ISP1161BM 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller
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ISP1181A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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