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參數資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 90/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
90 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
14.1.2
Write/Read Device Address
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in
Table 77
.
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the Address Register (accessible by the microcontroller) is not altered by
the bus reset. In response to the standard USB request Set Address the firmware
must issue a Write Device Address command, followed by sending an empty packet
to the host. The
new
device address is activated when the host acknowledges the
empty packet.
Code (Hex): B6/B7 —
write/read Address Register
Transaction —
write/read 1 word
14.1.3
Write/Read Mode Register
This command is used to access the ISP1161’s DC Mode Register, which consists of
1 byte (bit allocation: see
Table 78
). In 16-bit bus mode the upper byte is ignored.
The Mode Register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 —
write/read Mode Register
Transaction —
write/read 1 word
Table 76: Endpoint Configuration Register: bit description
Bit
Symbol
Description
7
FIFOEN
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
6
EPDIR
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write)
5
DBLBUF
A logic 1 indicates that this endpoint has double buffering.
4
FFOISO
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
3 to 0
FFOSZ[3:0]
Selects the FIFO size according to
Table 8
Table 77: Address Register: bit allocation
Bit
7
Symbol
DEVEN
Reset
0
Access
R/W
6
5
4
3
2
1
0
DEVADR[6:0]
0
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 78: Address Register: bit description
Bit
Symbol
7
DEVEN
6 to 0
DEVADR[6:0]
Description
A logic 1 enables the device.
This field specifies the USB device address.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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