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參數(shù)資料
型號: ISP1161BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 27/127頁
文件大小: 2762K
代理商: ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
27 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
9.4 HC’s internal FIFO buffer RAM structure
9.4.1
Partitions
According to the Universal Serial Bus Specification Rev 1.1 there are four types of
USB data transfers: Control, Bulk, Interrupt and Isochronous.
The HC’s internal FIFO buffer RAM is of a physical size of 4 kbytes. This internal
FIFO buffer RAM is used for transferring data between the microprocessor and USB
peripheral devices. This on-chip buffer RAM can be partitioned into two areas:
Acknowledged Transfer List (ATL) buffer and Isochronous (ISO)Transfer List (ITL)
buffer. The ITL buffer is a Ping-pong structured FIFO buffer RAM that is used to keep
the payload data and their PTD header for Isochronous transfers. The ATL buffer is a
non Ping-pong structured FIFO buffer RAM that is used for the other three types of
transfers.
For the ITL buffer, it can be further partitioned into ITL0 and ITL1 for the Ping-Pong
structure. The ITL0 buffer and ITL1 buffer always have the same size. The
microprocessor can put ISO data into either the ITL0 buffer or the ITL1 buffer. When
the microprocessor accesses an ITL buffer, the HC can take over another ITL buffer
at the same time. This architecture can improve the ISO transfer performance.
The Host Controller Driver can assign the logical size for ATL buffer and ITL buffers at
any time, but normally at initialization after power-on reset, by setting the
HcATLBufferLength register (2BH - Read, ABH - Write) and HcITLBufferLength
register (2AH - Read, AAH - Write), respectively. However, the total length (ATL buffer
+ ITL buffer) should not exceed 4 kbytes, the maximum RAM size.
Figure 26
shows
the partitions of the internal FIFO buffer RAM. When assigning buffer RAM sizes,
follow this formula:
ATL buffer length + 2
×
(ITL buffer size)
1000H (that is, 4 kbytes)
where: ITL buffer size = ITL0 buffer length = ITL1 buffer length
The following assignments are examples of legal uses of the internal FIFO buffer
RAM:
ATL buffer length = 800H, ITL buffer length = 400H.
This is the maximum use of the internal FIFO buffer RAM.
TotalBytes[9:0]
R
Specifies the total number of bytes to be transferred with this data structure. For Bulk and
Control only, this can be greater than MaximumPacketSize.
00
SETUP
01
OUT
10
IN
11
reserved
The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then
Format = 0. If this is an Isochronous endpoint, then Format = 1.
The is the USB address of the function containing the endpoint that this PTD refers to.
DirectionPID[1:0]
R
Format
R
FunctionAddress[6:0]
R
Table 5:
Symbol
Philips Transfer Descriptor (PTD): bit description
…continued
Access
Description
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