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參數資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 79/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
79 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
Code (Hex): 24 —
read
Code (Hex): A4 —
write
Table 50: Hc
μ
PInterrupt Register: bit allocation
Bit
15
Symbol
Reset
Access
Bit
7
Symbol
reserved
14
13
12
11
10
9
8
reserved
00H
R/W
6
5
4
3
2
1
0
ClkReady
HC
Suspended
0
OPR_Reg
reserved
AllEOT
Interrupt
0
ATLInt
SOFITLInt
Reset
Access
0
0
0
0
0
0
R/W
Table 51: Hc
μ
PInterrupt Register: bit description
Bit
Symbol
15 to 8
-
7
-
6
ClkReady
Description
reserved
reserved
0 —
no event
1 —
clock is ready. (After a wakeup is sent, there is a wait for clock
ready. Maximum is 1 ms, and typical is 160
μ
s)
0 —
no event
1 —
the HC has been suspended and no USB activity is sent from
the microprocessor for each ms. When the microprocessor wants
to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are
suspended, then the HC stops sending SOF; the HC is suspended
by having the HcControl register written into.
read HcControl and HcInterrupt registers to detect type of interrupt
on the HC (if the HC requires the Operational register to be
updated)
reserved
0 —
no event
1 —
implies that data transfer has been finished via PIO transfer or
DMA transfer. Occurrence of internal or external EOT will set this
bit.
0 —
no event
1 —
implies that the microprocessor must read ATL data from the
HC. This requires that the HcBufferStatus register must first be
read. The time for this interrupt depends on the number of clocks
bit set for USB activities in each ms.
0 —
no event
1 —
implies that SOF indicates the 1 ms mark. The ITL buffer that
the HC has handled must be read. To know the ITL buffer status,
the HcBufferStatus Register must first be read. This is for
microprocessor to get ISO data to or from the HC. For more
information, see
Section 9.5 on page 33
6th paragraph.
5
HCSuspen
ded
4
OPR_Reg
3
2
-
AllEOTInter
rupt
1
ATLInt
0
SOFITLInt
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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