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參數(shù)資料
型號： P90CL301
廠商： NXP Semiconductors N.V.
英文描述： Low voltage 16-bit microcontroller
中文描述： 低電壓16位微控制器
文件頁數(shù)： 16/92頁
文件大小： 526K
代理商： P90CL301
1996 Dec 11
16
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
6.7
Interrupt controller
An interrupt controller handles all internal and external
interrupts. It delivers the interrupt with the highest priority
level to the CPU. The following interrupt requests are
generated by the on-chip peripherals:
I
2
C-bus
UARTs: received data / transmitted data
Timers: two flags for the timers T0 and T1
ADC: analog-to-digital conversion completed.
The external interrupt requests are generated with the pins
NMIN and the seven external interrupts INT0 to INT6.
6.7.1
I
NTERRUPT ARBITRATION
The interrupt priority levels are programmable with a value
between 0 and 7. Level 7 has the highest priority, level 0
disables the corresponding interrupt source. In case of
interrupt requests of equal priority level at the same time a
hardware priority mechanism gives priority order as shown
in Table 16.
The execution of interrupt routines can be interrupted by
another interrupt request of a higher priority level. In 68070
mode (SYSCON bit IM = 1) when an interrupt is serviced
by the CPU, the corresponding level is loaded into the
Status Register. This prevents the current interrupt from
getting interrupted by any other interrupt request on the
same or a lower priority level. If IM is reset, priority level 7
will always be loaded into the Status Register and so the
current interrupt cannot be interrupted by an interrupt
request of a level less than 7.
Each on-chip peripheral unit including the eight interrupt
lines generate only auto-vectored interrupts. No
acknowledge is necessary. For external interrupts the
vectors 25 to 31 are used, for on-chip peripheral circuits a
second table of 7 vectors are used (57 to 63); see
Section 7.3.2.
Table 16
Priority order
6.7.2
E
XTERNAL LATCHED INTERRUPTS
NMIN and INT0 to INT6 are 8 external interrupt inputs.
These pins are connected to the interrupt function only
when the corresponding bit in the SPCON control register
is set (see Section 8.2; Table 29). Seven interrupt inputs
INT0 to INT6 are edge sensitive on HIGH-to-LOW
transition and their priority levels are programmable.
The interrupt NMIN is non-maskable (except if it is
programmed as a port) and is also edge sensitive on
HIGH-to-LOW transition. The priority level of NMIN is fixed
to 7.
The external interrupts are controlled by the registers
LIR0 to LIR3; see Tables 17 and 18.
SIGNAL
PRIORITY ORDER
NMIN
INT6
INT5
INT4
INT3
INT2
INT1
INT0
I
2
C-bus
ADC
UART1 receiver
UART1 transmitter
UART0 receiver
UART0 transmitter
Timer 1
Timer 0
highest
lowest
6.7.2.1
Latched Interrupt Registers (LIR0 to LIR3)
Table 17
Latched Interrupt Registers
ADDRESS
REGISTER
7
6
5
4
3
2
1
0
FFF 8101H
FFF 8103H
FFF 8105H
FFF 8107H
LIR0
LIR1
LIR2
LIR3
PIR1
PIR3
PIR5
PIR7
IPL1.2
IPL3.2
IPL5.2
1
IPL1.1
IPL3.1
IPL5.1
1
IPL1.0
IPL3.0
IPL5.0
1
PIR0
PIR2
PIR4
PIR6
IPL0.2
IPL2.2
IPL4.2
IPL6.2
IPL0.1
IPL2.1
IPL4.1
IPL6.1
IPL0.0
IPL2.0
IPL4.0
IPL6.0
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