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參數(shù)資料
型號： P90CL301
廠商： NXP Semiconductors N.V.
英文描述： Low voltage 16-bit microcontroller
中文描述： 低電壓16位微控制器
文件頁數(shù)： 47/92頁
文件大小： 526K
代理商： P90CL301
1996 Dec 11
47
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.4
I
2
C-bus interface
The serial port supports the twin line I
2
C-bus. The I
2
C-bus
consists of a data line SDA and a clock line SCL. These
lines also function as I/O port lines P11 and P10
respectively (always open drain). The system is unique
because data transport, clock generation, address
recognition and bus control arbitration are all controlled by
hardware. The I
2
C-bus serial I/O has complete autonomy
in byte handling and operates in four modes:
Master transmitter mode
Master receiver mode
Slave transmitter mode
Slave receiver mode.
These functions are controlled by the SCON register.
SSTA is the Status Register whose contents may be used
as a vector to various service routines. SDAT is the data
shift register and SADR the slave address register. Slave
address recognition is performed by hardware.
For more details on the I
2
C-bus functions, see user
manual “The I
2
C-bus and how to use it (including
specifications)”; order number 9398 393 40011.
12.5
Serial Control Register (SCON)
Table 66
Serial Control Register (address FFFF 8207H)
Table 67
Serial Control Register SCON bits
7
6
5
4
3
2
1
0
CR2
ENS
STA
STO
SI
AA
CR1
CR0
BIT
SYMBOL
DESCRIPTION
7, 1 and 0
CR2 to CR0 These three bits determine the serial clock frequency when SIO is in a master mode
function of the peripheral clock FCLK (see Tables 68 and 69).
ENS
Enable serial I/O
. If ENS = 0, the serial interface I/O is disabled and reset; if ENS = 1,
the serial interface is enabled.
STA
Start flag
. When this bit is set in slave mode, the hardware checks the I
2
C-bus and
generates a START condition if the bus is free or after the bus becomes free. If the
device operates in master mode it will generate a repeated START condition.
STO
Stop flag
. If this bit is set in the master mode a STOP condition is generated. A STOP
condition detected on the I
2
C-bus clears this bit. The STOP bit may also be set in slave
mode in order to recover from an error condition. In this case no STOP condition is
generated to the I
2
C-bus, but the hardware releases the SDA and SCL lines and
switches to the not selected slave receiver mode. The STOP flag is cleared by the
hardware.
SI
Serial Interrupt flag
. This flag is set, and an interrupt is generated, after any of the
following events occur:
A START condition is generated in master mode.
The own slave address has been received during AA = 1.
The general call address has been received while bit SADR.0 = 1 and AA = 1.
A data byte has been received or transmitted in master mode.
A data byte has been received or transmitted as selected slave.
A STOP or START condition is received as selected slave receiver or transmitter.
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must
be reset by software.
6
5
4
3
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