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參數資料
| 型號： | P90CL301 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 低電壓16位微控制器 |
| 文件頁數： | 26/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301 |
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1996 Dec 11
26
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
7.6
CPU interrupt processing
The general interrupt handling mechanism is described in
Section 6.7. An interrupt controller handles all interrupts,
resolves the priority problem and passes the highest level
interrupt to the CPU.
The CPU interrupt handling follows the same basic rules
as in the MC68000. However, some remarks must be
made:
Interrupts with a priority level equal to or lower than the
current priority level will not be accepted.
During the acknowledge cycle of an interrupt, the IPL
bits of the Status Register are set to the priority of the
acknowledged interrupt or to 7. An exception occurs
when bit IM = 0 (SYSCON bit 5). In this case level 7 is
loaded into the Status Register (see Section 6.4;
Table 14).
If the priority level of the pending interrupt is greater than
the current processor priority then:
The exception processing sequence is started
A copy of the Status Register is saved
The privilege level is set to Supervisor state
Tracing is suppressed
The priority level of the processor is set to that of the
interrupt being acknowledged or to 7 depending on the
IM flag in the System Control Register.
The processor then gets the vector number from the
interrupting device, classifies it as an interrupt
acknowledge and displays the interrupt level number
being acknowledged on the internal address bus.
As all P90CL301BFH interrupts are auto-vectored, the
processor internally generates a vector number
corresponding to the interrupt level number.
The processor starts normal exception processing by
saving the format word, program counter and Status
Register on the Supervisor stack. The value of the vector
in the format word is an internally generated vector number
multiplied by 4 (format is all zeros). The program counter
value is the address of the instruction that would have
been executed if the interrupt had not been present. Then
the interrupt vector contents are fetched and loaded into
the program counter. The interrupt handling routine starts
with normal instruction execution.
7.7
Bus arbitration
If the HALT pin is held LOW with RESET HIGH the CPU
will stop after completion of the current bus cycle. As long
as HALT is LOW, all control signals are inactive and all
3-state lines are placed in the high-impedance state. If the
HALT pin is held LOW during the transfer of a word in 8-bit
mode, the CPU will continue the transfer of the two bytes
before it halts.
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相關代理商/技術參數 |
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