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參數資料
| 型號： | P90CL301 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 低電壓16位微控制器 |
| 文件頁數： | 24/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301 |
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1996 Dec 11
24
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
7.3.3
I
NSTRUCTION TRAPS
Traps are exceptions caused by instructions arising from
CPU recognition of abnormal conditions during instruction
execution or from instructions whose normal behaviour is
to cause traps.
Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception and is
useful for implementing system calls for User Programs.
The TRAPV and CHK instructions force an exception if the
User Program detects a run-time error, possibly an
arithmetic overflow or a subscript out of bounds.
The signed divide (DIVS) and unsigned divide (DIVU)
instructions will force an exception if a divide-by-zero
operation is attempted.
7.3.4
I
LLEGAL AND UNIMPLEMENTED INSTRUCTIONS
Illegal instruction is the term used to refer to any word that
is not the first word of a legal instruction. During execution,
if such an instruction is fetched an illegal exception occurs.
Words with bits 15 to 12 equal to ‘1010’ or ‘1111’ are
defined as unimplemented instructions and separate
exception vectors are allocated to these patterns for
efficient emulation. This facility means the operating
system can detect program errors, or can emulate
unimplemented instructions in software.
7.3.5
P
RIVILEGE VIOLATIONS
To provide system security, various instructions are
privileged and any attempt to execute one of the privileged
instruction while the CPU is in the User state provokes an
exception. The privileged instructions are:
STOP
RESET
RTE
MOVE to SR
AND (word) immediate to SR
EOR (word) immediate to SR
OR (word) immediate to SR
MOVE to USP.
7.4
Tracing
The CPU includes a facility to trace instructions one by one
to assist in program development. In the trace state, after
each instruction is executed, an exception is forced so that
the debugging program can monitor execution of the
program under test.
The trace facility uses the T-bit in the Supervisor part of the
Status Register. If the T-bit is cleared, tracing is disabled
and instructions are executed normally. If the T-bit is set at
the beginning of the execution of an instruction, a trace
exception will be generated once the instruction has been
executed. If the instruction is not executed, either because
of an interrupt, or because the instruction is illegal or
privileged, the trace exception does also not occur if the
instruction is aborted by a reset, bus error, or address error
exception. If the instruction is executed, and an interrupt is
pending, the trace exception is processed before the
interrupt. If the execution of an instruction forces an
exception, the forced exception is processed before the
trace exception.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP
instruction, while tracing is enabled. First the trap
exception is processed, followed by the trace exception,
and finally the interrupt handling routine.
7.5
Stack format
The stack format for exception processing is similar to the
MC68010 although the instruction stored is not the same,
due to the different architecture. To handle this format the
P90CL301BFH differs from the MC68000 in that:
The stack format is changed.
The minimum number of words put into or restored from
stack is 4 (MC68010 compatible, not 3 as with the
MC68000).
The RTE instruction decides (with the aid of the 4 format
bits) whether or not more information has to be restored
as follows:
– The P90CL301BFH long format is used for bus errors
and address error exceptions.
– All other exceptions use the short format.
If another format code, other than those listed above, is
detected during the restored action, a FORMAT ERROR
occurs.
If the user wants to finish the instruction in which the bus
or address error occurred, the P90CL301BFH format must
be used on RTE. If no changes to the stack are required
during exception processing, the stack format is
transparent to the user.
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相關代理商/技術參數 |
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