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參數(shù)資料
型號: P90CL301
廠商: NXP Semiconductors N.V.
英文描述: Low voltage 16-bit microcontroller
中文描述: 低電壓16位微控制器
文件頁數(shù): 35/92頁
文件大小: 526K
代理商: P90CL301
1996 Dec 11
35
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
11.5
Timer Control Registers
The Timer 0 (T0) is controlled via Timer 0 Control Registers (T0CRH and T0CRL), and Timer 1 (T1) via Timer 1 Control
Registers (T1CRH and T1CRL); see Fig.10 and Tables 41 to 44. The default value after a CPU reset for all bits of
T0CRH; T1CRH; T0CRL and T1CRL is a logic 0.
Table 41
Timer Control Registers T0CRH and T1CRH
Table 42
Timer Control Registers T0CRL and T1CRL
Table 43
Description of T0CRH; T1CRH; T0CRL and T1CRL bits
ADDRESS
REGISTER
15
14
13
12
11
10
9
8
FFFF 8300H
FFFF 8310H
T0CRH
T1CRH
ECM2
C2M2
C2M1
C2M0
ECM1
C1M2
C1M1
C1M0
ADDRESS
REGISTER
7
6
5
4
3
2
1
0
FFFF 8301H
FFFF 8311H
T0CRL
T1CRL
ECM0
C0M2
C0M1
C0M0
ETOV
GATE
C/TN
RUN
BIT
SYMBOL
DESCRIPTION
15, 11 and 7
ECM2 to ECM0
Channel n interrupt enable
(n = 0 to 2);
ECMn = 0, the channel n interrupt is disabled;
ECMn = 1, the channel n interrupt is enabled.
C2M2 to C2M0
Channel mode
; see Table 44.
C1M2 to C1M0
C0M2 to C0M0
ETOV
Timer overflow interrupt enable
;
ETOV = 0, the timer overflow interrupt is disabled;
ETOV = 1, the timer overflow interrupt is enabled.
GATE
Gated external clock
;
GATE = 0, disable gate function;
GATE = 1, the prescaler increments only if the CP0 pin is HIGH for each rising edge
transition of CLK0 if C/TN = 1 or with FCLK if C/TN = 0.
C/TN
Counter/timer mode;
C/TN = 0, timer mode; the prescaler is incremented on the rising edge of the
peripheral clock (FCLK);
C/TN = 1, counter mode; the prescaler increments on the rising edge of CLK0 for
Timer 0 (CLK1 for Timer 1).
RUN
Timer run enable
;
RUN = 0, timer prescaler stopped and registers value held;
RUN = 1, when set the prescaler and counter are loaded and the prescaler is then
incremented.
14 to 12
10 to 8
6 to 4
3
2
1
0
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