
1996 Dec 11
9
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
6.2.1
C
HIP
S
ELECT
C
ONTROL
R
EGISTERS
(CS0N
TO
CS7N)
Table 3
Chip Select Control Registers CS0N to CS7N (address FFFF 8A00H to FFFF 8A0CH)
Table 4
Description of CS0N to CS7N bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
M22
M21
M20
M19
RW1
RW0
MD1
MD0
A23
A22
A21
A20
A19
WS2
WS1
WS0
BIT
SYMBOL
DESCRIPTION
15 to 12
11 to 10
9 to 8
7 to 3
M22 to M19
RW1 to RW0 Read/Write bus control (R/W); see Table 6.
MD1 to MD0 MODE selection; see Table 7.
A23 to A19
Decoded base address; this should be a multiple of the block size (other codes are
reserved for test or reset state); after reset: A23 to A19 = 11111 except for CSBT.
WS2 to WS0 Wait states 0 to 6 (see Table 8); 7 wait states for DTACK to be pulled LOW by the
external address decoding circuitry. The default value after reset is ‘110B’ for CSBT and
‘111B’ for the other chip-selects.
Address mask for block size selection; see Table 5.
2 to 0
Table 5
Address mask for block size selection
Table 6
Read/Write bits (R/W)
Table 7
Mode selection
M22
M21
M20
M19
BLOCK SIZE
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
512 kbytes
1 Mbyte
2 Mbytes
4 Mbytes
8 Mbytes; default value
after a CPU reset
RW1
RW0
FUNCTION
0
0
1
1
0
1
0
1
Read only with length of AS
Write only with length of DS
Write only with length of AS
Read/write with length of AS; default
value after a CPU reset
MD1
MD0
FUNCTION
0
0
1
1
0
1
0
1
Alternate function
Low byte access only
High byte access only
Word access; default value after a CPU
reset
Table 8
Wait states selection
Note
1.
The default value after a CPU reset.
WS2
WS1
WS0
WAIT STATES
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
(1)