
1996 Dec 11
37
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
11.7
Watchdog Timer
The P90CL301BFH contains a Watchdog Timer consisting
of a 13-bit prescaler and an 8-bit timer WDTIM.
The prescaler is incremented by the peripheral clock.
The 8-bit timer is incremented every 8192 cycles of the
peripheral clock FCLK.
If the FCLK frequency is 2 MHz, the Watchdog Timer can
operate in the range of 4.1 ms up to 1 s. The Watchdog
Timer is disabled after reset. It can be enabled by writing
any value to the WDCON register. The only way to disable
a running Watchdog Timer is to reset the P90CL301BFH.
When a timer overflow occurs the microcontroller will be
reset (except registers SYSCON, PCON, PRL and PRH
which will not be reset). To prevent an overflow of the
Watchdog Timer, the User Program must reload the
Watchdog register within a period shorter than the
programmed timer interval.
This timer interval is determined by the 8-bit timer value
written to the register WDTIM.
For FCLK in MHz, the Watchdog period is:
The Watchdog Timer is controlled by the register WDCON.
A value of A5H in WDCON clears both the prescaler and
timer WDTIM. After reset, WDCON contains A5H.
Every value other than A5H in WDCON enables the
Watchdog Timer. Since the bit 0 of the WDCON input is
tied to a logic 0 by hardware during write operations on
WDCON, the reset value A5H can not be programmed
again and can only be restored by a reset.
Timer WDTIM can be written only if WDCON has
previously been loaded with 5AH, otherwise WDTIM and
the prescaler are not affected. A successful write operation
to WDTIM also clears the prescaler and clears WDCON.
Only the values A5H or 5AH are stored, all other values
are stored with a dummy value 00H.
256
WDTIM
–
(
)
FCLK
μ
s
×
Fig.11 Watchdog Timer block diagram.
handbook, full pagewidth
MBG325
INTERNAL BUS
PRESCALER
13-BIT
COUNTER REGISTER
8-BIT
WDCON
REGISTER
WDTIM
8-BIT RELOAD
REGISTER
FCLK
FCLK/8192
enable
overflow Internal
reset