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參數(shù)資料
| 型號： | P90CL301 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 低電壓16位微控制器 |
| 文件頁數(shù)： | 54/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301 |
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1996 Dec 11
54
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
14 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consist of a 4 input analog
multiplexer and an analog-to-digital converter (ADC) with
8-bit resolution. The analog reference voltage V
ref(A)
and
the analog supplies V
DDA
, V
SSA
are connected via
separate input pins.
The conversion time takes 24 periods of the secondary
peripheral clock FCLK2 (see Section 6.6). The maximum
value of the FCLK2 clock is dependant on the supply
voltage (see Section 20).
As the ADC is based on a successive approximation
algorithm using a resistor scale connected to V
ref(A)
and
V
SSA
, a continuous current flows in this resistor.
By resetting the EADC bit in the control register ADCON or
by entering Power-down it is possible to switch off this
current to reduce the static power consumption.
The ADC is controlled using the ADCON control register.
Input channels are selected by the analog multiplexer
function of register bits ADCON.0 and ADCON.1.
The completion of the 8-bit ADC conversion is flagged by
ADCI in the ADCON register and the result is stored in the
register ADCDAT (address FFFF 8809H). The result of a
completed conversion remains unaffected provided ADCI
is HIGH. While ADCS or ADCI are HIGH, a new ADC start
will be blocked and consequently lost. An ADC conversion
already in progress is aborted when Power-down mode is
entered.
14.1
ADC Control Register (ADCON)
Table 86
ADC Control Register (address FFFF 8807H)
Table 87
Description of ADCON bits
Table 88
Operation of ADCI and ADCS
7
6
5
4
3
2
1
0
EADC
ADCI
ADCS
A1
A0
BIT
SYMBOL
EADC
DESCRIPTION
7, 5 and 2
6
Reserved; set to LOW.
ADC enable
. If EADC = 1, then ADC is enabled. If EADC = 0, then ADC is disabled;
the resistor reference is switched off to save power even while the CPU is operating.
ADC interrupt flag
. This flag is set when an ADC conversion result is ready to be read.
An interrupt is invoked if the level IPLA is different from ‘0’. The flag must be cleared by
software (it cannot be set by software). The ADCI bit must be cleared before a new
conversion is started.
ADC start and status
. Setting this bit starts a conversion. The logic ensures that this
signal is HIGH while the conversion is in progress. On completion, ADCS is reset at the
same time the interrupt flag ADCI is set. ADCS cannot be reset by software.
Analog input select
. This binary coded address selects one of the four analog inputs
ADC0 to ADC3. It can only be changed when ADCI and ADCS are both LOW. A1 is the
MSB; e.g. ‘11’ selects analog input channel ADC3.
4
ADCI
3
ADCS
1, 0
A1, A0
ADCI
ADCS
OPERATION
0
0
1
1
0
1
0
1
ADC not busy, a conversion can be started.
ADC busy, start of a new conversion is blocked.
Conversion completed, start of a new conversion is blocked.
Intermediate status for a maximum of one machine cycle before conversion is
completed (ADCI = 1, ADCS = 0).
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