
1996 Dec 11
39
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.1.2
UART C
ONTROL
R
EGISTERS
SCON0
AND
SCON1
The registers SCON0 and SCON1 control UART0 and UART1 modes respectively, and contain the interrupt flags.
Table 49
UART Control Registers SCON0 and SCON1
Table 50
Description of register SCON0 and SCON1 bits
Table 51
Mode defined by bits SM0 and SM1
ADDRESS
REGISTER
7
6
5
4
3
2
1
0
FFFF 8603H
FFFF 8607H
SCON0
SCON1
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
BIT
SYMBOL
DESCRIPTION
7 to 6
5
SM0 to SM1
SM2
Mode bits; see Table 51.
Multiprocessor
; enable the multiprocessor communication feature in Modes 2 and 3.
If SM2 is set the RI will not be activated if the received 9
th
data bit RB8 = 0. In Mode 1,
if SM2 is set the RI will not be activated if a valid stop bit is not received. In Mode 0,
SM2 should be a logic 0.
Receive enable
; enables serial reception; set and cleared by software.
Transmit extra bit
; 9
th
data bit that will be transmitted in Modes 2 and 3; set and
cleared by software.
Receive extra bit
; in Modes 2 and 3, RB8 is the 9
th
bit received. In Mode 1, if SM2 = 0,
RB8 is the stop bit which is received.
Transmit interrupt
; it is set by hardware at the end of the 8
th
bit time in Mode 0, or
halfway through the stop bit in the other modes (except: see bit SM2). TI must be
cleared by software (cannot be set by software). By writing a logic 1 the flags stay
unchanged. In order to clear a particular flag one has to write a logic 0 to the
corresponding position and a logic 1 to the others. One should avoid to use the
instruction BCLR, which can reset accidentally several flags.
Receive interrupt
; set by hardware at the end of the 8
th
bit time in Mode 0, or halfway
through the stop bit in the other modes (except: see SM2). RI must be cleared by
software (cannot be set by software). By writing a logic 1 the flags stay unchanged. In
order to clear a particular flag one has to write a logic 0 to the corresponding position
and a logic 1 to the others. One should avoid to use the instruction BCLR, which can
reset accidentally several flags.
4
3
REN
TB8
2
RB8
1
TI
0
RI
SM0
SM1
MODE
DESCRIPTION
0
0
1
1
0
1
0
1
0
1
2
3
shift register;
1
6
×
CLK
8-bit UART; BGCLK0 and BGCLK1
9-bit UART;
1
16
×
CLK
9-bit UART; BGCLK0 and BGCLK1