
1996 Dec 11
36
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 44
Description of channel mode; n = 0 to 5; X = don’t care
11.6
Timer Status Registers
Four events can occur: a timer overflow or three channel matches/captures. These event flags are stored in the 4-bit
Timer 0 Status Register (T0SR for T0) and Timer 1 Status Register (T1SR for T1). They can be cleared by software but
cannot be set. By writing a logic 1 the flags stay unchanged. In order to clear a particular flag one has to write a logic 0
to the corresponding position and logic 1s to the others. One should avoid to use the instruction BCLR, which can reset
accidentally several flags.
11.6.1
T
IMER
0 S
TATUS
R
EGISTER
(T0SR)
Table 45
Timer 0 Status Register (address FFFF 830DH)
Table 46
Description of T0SR bits
11.6.2
T
IMER
1 S
TATUS
R
EGISTER
(T1SR)
Table 47
Timer 1 Status Register (address FFFF 831DH)
Table 48
Description of T1SR bits
CnM2
CnM1
CnM0
DESCRIPTION
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
channel n inhibited
channel n capture on LOW-to-HIGH transition of pin CPn
channel n capture on HIGH-to-LOW transition of pin CPn
channel n capture on any transitions of pin CPn
channel compare mode
7
6
5
4
3
2
1
0
C2F
C1F
C0F
TOV
BIT
SYMBOL
C2F to C0F
DESCRIPTION
7 to 4
3 to 1
Reserved.
Channel n event flag (n = 2 to 0); CnF = 0, no event (default value after a CPU reset).
CnF = 1, capture mode: a capture occurred.
Timer Overflow Flag; TOV = 0, no overflow (default value after a CPU reset).
TOV = 1, timer overflow occurred.
0
TOV
7
6
5
4
3
2
1
0
C5F
C4F
C3F
TOV
BIT
SYMBOL
C5F to C3F
DESCRIPTION
7 to 4
3 to 1
Reserved.
Channel n event flag (n = 5 to 3); CnF = 0, no event (default value after a CPU reset).
CnF = 1, capture mode: a capture occurred.
Timer Overflow Flag; TOV = 0, no overflow (default value after a CPU reset).
TOV = 1, timer overflow occurred.
0
TOV