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參數資料
| 型號： | P90CL301 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 低電壓16位微控制器 |
| 文件頁數： | 18/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301 |
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1996 Dec 11
18
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
6.8
Power reduction modes
The P90CL301BFH supports three power reduction
modes. A Power-down mode where the clock is frozen, a
Standby mode where only the CPU is stopped, and an Idle
mode where the external clock is divided by 512
(see Fig.4).
6.8.1
P
OWER
-
DOWN MODE
The Power-down operation freezes the oscillator. It can
only be activated by setting the PD bit in the SYSCON
register and thereafter execute the STOP instruction.
The instruction flow to enter the Power-down mode is:
BSET #PD, SYSCON
STOP #$2700.
In this state all the register contents are preserved.
The CPU remains in this state until an internal reset occurs
or a LOW level is present on any of the external interrupt
pins INT0 to INT6 or NMIN. If the wake-up is done via an
external interrupt, the processor will first execute an
external interrupt of level 7. If the IPL level in the LIR
register is set to 7, a second interrupt of level 7 will be
executed. It is preferable to set the IPL to 0.
In Power-down mode V
DD
may be reduced to minimize
power consumption. However, the supply voltage must not
be reduced until Power-down mode is active, and must be
restored before a external reset or an interrupt is activated.
In case of an external reset, the pin should be held active
until the external oscillator has restarted and stabilized.
In case of an external interrupt wake-up, anyINTn or NMIN
pin should go LOW and the corresponding bit ESn
(n = 0 to 7) in register SPCON should be set. If the DOFF
bit in the SYSCON is not set, an internal delay counter
ensures that the internal clock is not active before
1536 clock cycles. After that time the oscillator is stable
and normal exception processing can be executed.
The PD bit is cleared automatically during the wake-up.
In order to have a fast start-up the DOFF bit should be set,
switching off the delay counter and enabling the immediate
clocking and restart of the controller.
For minimum power consumption during Power-down
mode, the address and data pins should be pulled HIGH
externally or bit BPE in register SYSCON should be set
(i.e. internal pull-ups enabled).
6.8.2
S
TANDBY MODE
When the STBY bit in the SYSCON register is set, the
CPU clock is stopped and the status of the processor is
frozen, however, the clocks of all other on-chip peripherals
are still running at the nominal frequency; these
peripherals are:
Timers
External and internal interrupts
UARTs and baud rate generator
I
2
C-bus interface
Watchdog Timer
PWMs
ADC.
The CPU exits this mode when an internal or external
interrupt is activated, and proceeds with the normal
program execution.
For minimum power consumption internal pull-ups on
address and data buses can be switched on by setting the
control bit BPE in the SYSCON register. The pull-ups
should be switched off in normal mode if not needed.
6.8.3
I
DLE MODE
In the Idle mode the crystal or external clock is divided by
a factor 512. The current is reduced drastically but the
controller continues to operate. This mode is entered by
setting the bit IDL in the SYSCON register. The next
instruction will be executed at a slower speed. To return to
normal mode the IDL bit should be reset.
It should be noted that all peripheral functions are also
slowed down, and some cannot be used normally, for
example UART, I
2
C-bus, ADC and PWM.
The Power-down mode can also be entered from the Idle
mode. After a wake-up the controller restarts in Idle mode.
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