
152
Agere Systems Inc.
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
9 SPE Mapper Registers
(continued)
Table 176. SPE_SPE_RX_THRES_CTL_DS3, Receive Elastic Store Threshold Control for DS3 (R/W)
Address
Bit
Name
Function
Reset
Default
0
0x4D
0x300A3
15
14:8
RSVD
Reserved.
SPE_RX_HIGH_THRES_DS3[6:0]
Receive Elastic Store High Threshold for
DS3.
Programmable threshold controlling posi-
tive justifications.
RSVD
Reserved.
SPE_RX_LOW_THRES_DS3[6:0]
Receive Elastic Store Low Threshold for
DS3.
Programmable threshold controlling nega-
tive justifications.
7
0
6:0
0x4A
Table 177. SPE_SPE_TX_THRES_CTL_DS3, Transmit Elastic Store Threshold Control for DS3 (R/W)
Address
Bit
Name
Function
Reset
Default
0
0x38
0x300A4
15
14:8
RSVD
Reserved.
SPE_TX_HIGH_THRES_DS3[6:0]
Transmit Elastic Store High Threshold for
DS3.
Programmable threshold controlling posi-
tive justifications.
RSVD
Reserved.
SPE_TX_LOW_THRES_DS3[6:0]
Transmit Elastic Store Low Threshold for
DS3
. Programmable threshold controlling nega-
tive justifications.
7
0
6:0
0X36
Table 178. SPE_SPE_OV_UN_FIFO_THRES FIFO Overflow and Underflow Thresholds (R/W)
Address
Bit
Name
Function
Reset
Default
0
0x1E
0x300B0
15:7
6:0
RSVD
Reserved
.
SPE_RX_OVUN_FLOW_THRES[6:0]
Receive FIFO Overflow/Underflow
Threshold.
Programmable threshold con-
trolling overflow/underflow event. If the write
minus the read address falls below this
value, then the overflow/underflow event will
be a 1. If the write minus the read address is
above this half of this value, then the over-
flow/underflow event will be a 1.
Reserved
.
0x300B1
15:7
6:0
RSVD
0
SPE_TX_OVUN_FLOW_THRES[6:0]
Transmit FIFO Overflow/Underflow
Threshold.
Programmable threshold con-
trolling overflow/underflow event. If the write
minus the read address falls below this
value, then the overflow/underflow event will
be a ‘1’. If the write minus the read address
is above this half of this value, then the over-
flow/underflow event will be a 1.
0x1E