
Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
339
Agere Systems Inc.
14 Digital Jitter Attenuation Controller Registers
(continued)
Table 488. DJA_E1PTRH
—
DJA_E1PTRL, E1 First-Order Loop Counter (R/W)
Table 489. DJA_DS1PTRH
—
DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W)
Table 490. DJA_DS1SELH—DJA_DS1SELL, DS1 E1 Mode Select (R/W)
Table 491. DJA_CLK_CTL1—DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W)
Address
Bit
Name
Function
Reset
Default
0x177000
0x70011
0x70012
15:5
4:0
15:0
RSVD
DJA_E1PTRADJCNT[20:16]
DJA_E1PTRADJCNT[15:0]
Reserved.
E1 First-Order Loop Count.
Count value that
determines the amount of time spent as a first-
order loop following a VT pointer adjustment in
E1 mode (see
Table 635 on page 580
).
Address
Bit
Name
Function
Reset
Default
0x11AB70
0x70013
0x70014
15:5
4:0
15:0
RSVD
DJA_DS1PTRADJCNT[20:16]
DJA_DS1PTRADJCNT[15:0]
Reserved.
DS1 First-Order Loop Count.
Count value that
determines the amount of time spent as a first-
order loop following a VT pointer adjustment in
DS1 mode (see
Table 635
).
Address
Bit
Name
Function
Reset
Default
0xFFFFFFF
0x70015
0x70016
15:12
11:0
15:0
RSVD
DJA_DS1SEL[28:17]
DJA_DS1SEL[16:1]
Reserved.
DS1 E1 Mode Select.
Control signal that deter-
mines the operating mode of each jitter attenua-
tion block (1 = DS1, 0 = E1).
Address
Bit
Name
Function
Reset
Default
0x70017
15:14
13:12
RSVD
Reserved.
Reference Clock Rate.
Control signal that indi-
cates that the input XCLK runs at 32 X (11) or
16 X (01) the line rate or exactly the line rate
(00).
Transmit Edge Select.
Control signal that deter-
mines on which edge of the clock the output
DS1/E1 data transitions (1 = rising edge).
Reserved.
Receive Edge Select.
Control signal that deter-
mines on which edge of the clock the input
DS1/E1 data is retimed (1 = rising edge).
DJA_BLUECLKD1[1:0]
111
0x70017
0x70018
11:0
15:0
DJA_TXEDGE[28:17]
DJA_TXEDGE[16:1]
0xFFFFFFF
0x70019
0x7001A
15:12
11:0
15:0
RSVD
DJA_RXEDGE[28:17]
DJA_RXEDGE[16:1]
0xFFFFFFF