
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
170
Agere Systems Inc.
10 VT/TU Mapper Registers
(continued)
Table 211. VT_TCTL[1—28], Transmit Control Per Channel (R/W)
Address
Bit
Name
Function
Reset
Default
0x0
0x0
0x200DC
—
0x200F7
15:13
12
RSVD
Reserved.
Transmit Path Enhanced RDI-V Enable.
Logic 1
enables enhanced RDI-V.
Enhanced RDI-V Source Selection.
Logic 1
activates software overwrite of the ERDI-V bits of
the Z7 byte. Otherwise, insertion is based on the
LOPOH serial channel or automatic generation.
RDI-V Source Selection.
Logic 1 activates soft-
ware overwrite of the RDI-V bit of the V5 byte.
Otherwise, insertion is based on the LOPOH
serial channel or automatic generation.
RFI-V Source Selection.
Logic 1 activates soft-
ware overwrite of the RFI-V bit of the V5 byte. If
VT_V5_INS[1—28] = 0 (
Table 212 on page 171
)
and the mapping is set to byte synchronous DS1,
a logic 0 enables automatic insertion of RFI-V. If
VT_V5_INS[1—28] = 1, a logic 0 inserts RFI-V
based on the LOPOH serial channel.
REI-V Enable.
Logic 1 activates automatic gener-
ation of REI-V. If VT_V5_INS[1—28] = 0, the gen-
eration is based on the received BIP-2 errors.
Otherwise, insertion is based on the LOPOH
serial channel.
Reserved.
AIS-V Insertion Control.
Logic 1 forces AIS-V to
be transmitted in the specified channel.
Transmit Path DS1/E1 Clock Edge Selection.
Logic 1 forces the DS1/E1 signals to be retimed
using the rising edge of the associated clock.
Logic 0 forces the DS1/E1 signals to be retimed
using the falling edge of the associated clock.
Tributary Loopback Selection.
Logic 1 acti-
vates tributary loopback.
Transmit Mapping Mode Control.
See
Table 570 on page 448
.
VT_TX_ERDI_EN[1—28]
11
VT_ERDI_EN[1—28]
0x0
10
VT_RDI_EN[1—28]
0x0
9
VT_RFI_EN[1—28]
0x0
8
VT_REI_EN[1—28]
0x0
7
6
RSVD
0
VT_AIS_INS[1—28]
0x0
5
VT_TX_CLKEDGE[1—28]
0x0
4
VT_LB_SEL[1—28]
0x0
3:0
VT_TX_MAPTYPE[1—28][3:0]
0x6