
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
538
Agere Systems Inc.
21 28-Channel Framer Block Functional Description
(continued)
The offset is further determined by the use of four bits: FRM_THALFOFF, FRM_RHALFOFF, FRM_TQUAROFF,
and FRM_RQUAROFF (
Table 430 on page 299
). When the CHI clock and data rate are the same (FRM_CMS =
0), setting FRM_THALFOFF and FRM_RHALFOFF bits will increase the clock edge offset, CEX and CER, by one.
When the CHI clock is twice the data rate (FRM_CMS = 1), setting the FRM_THALFOFF and FRM_RHALFOFF
bits will increase the clock edge offset by two, and setting the FRM_TQUAROFF and FRM_RQUAROFF bits will
increase the clock offset by one.
The byte offsets FRM_TBYOFF[6:0] and FRM_RBYOFF[6:0] (
Table 430
) increment the offset one byte at a time.
When FRM_CMS = 0, the offset will increment by 16 clock edges; when FRM_CMS = 1, the offset will increment
by 32 clock edges.
Figure 74
shows an example of the relative timing of CHI 2.048 Mbits/s data with the following parameters:
I
FRM_CMS = 0, FRM_TFSCKE, FRM_RFSCKE = 0, FRM_TQUAROFF = 0, FRM_RQUAROFF = 0.
I
FRM_THALFOFF = 1, FRM_TOFF[2:0] = 001, FRM_TBYOFF[6:0] = 0000000.
I
FRM_RHALFOFF = 0, FRM_ROFF[2:0] = 010, FRM_RBYOFF[6:0] = 0000000.
5-8983(F)
Note: CEX = 3 and CER = 4, Respectively
Figure 74. TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 0
Figure 75
shows an example of the relative timing of CHI 2.048 Mbits/s data with the following parameters:
I
FRM_CMS = 1, FRM_TFSCKE = 0, FRM_RFSCKE = 0.
I
FRM_THALFOFF = 1, FRM_TQUAROFF = 1, FRM_TOFF[2:0] = 000, FRM_TBYOFF[6:0] = 0000000.
I
FRM_RHALFOFF = 1, FRM_RQUAROFF = 0, FRM_ROFF[2:0] = 001, FRM_RBYOFF[6:0] = 0000000.
CHI FRAME SYNC IS SAMPLED ON THE FALLING EDGE
1
2
3
4
5
6
7
8
BIT 0, TS 0
BIT 1, TS 0
BIT 2, TS 0
CEX = 3
CER = 4
BIT 0, TS 0
BIT 1, TS 0
BIT 2, TS 0
HIGH IMPEDANCE
RCHIDATA
TCHIDATA
TCHIFS/
RCHIFS
TCHICK/
RCHICK