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參數資料
| 型號： | TLV320DAC3100IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數： | 28/97頁 |
| 文件大小： | 1134K |
| 代理商： | TLV320DAC3100IRHBT |
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SLAS671 – FEBRUARY 2010
www.ti.com
5.5.4.2
DRC Hysteresis
DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be
programmed to represent values between 0 dB and 3 dB in steps of 1 dB. DRC hysteresis provides a
programmable window around the programmed DRC threshold that must be exceeded for the disabled
DRC to become enabled, or the enabled DRC to become disabled. For example, if the DRC threshold is
set to –12 dBFS and the DRC hysteresis is set to 3 dB, then if the gain compression in the DRC is
inactive, the output of the DAC digital volume control must exceed –9 dBFS before gain compression due
to the DRC is activated. Similarly, when the gain compression in the DRC is active, the output of the DAC
digital volume control must fall below –15 dBFS for gain compression in the DRC to be deactivated. The
DRC hysteresis feature prevents the rapid activation and de-activation of gain compression in the DRC in
cases when the output of the DAC digital volume control rapidly fluctuates in a narrow region around the
programmed DRC threshold. By programming the DRC hysteresis as 0 dB, the hysteresis action is
disabled.
The recommended value of DRC hysteresis is 3 dB.
5.5.4.3
DRC Hold Time
DRC hold time is intended to slow the start of decay for a specified period of time in response to a
decrease in energy level. To minimize audible artifacts, it is recommended to set the DRC hold time to 0
through programming page 0 / register 69, bits D6–D3 = 0000.
5.5.4.4
DRC Attack Rate
When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain
applied in the DAC digital volume control is progressively reduced to avoid the signal from saturating the
channel. This process of reducing the applied gain is called attack. To avoid audible artifacts, the gain is
reduced slowly with a rate equaling the attack rate, programmable via page 0 / register 70, bits D7–D4.
Attack rates can be programmed from 4-dB gain change per sample period to 1.2207e–5-dB gain change
per sample period.
Attack rates should be programmed such that before the output of the DAC digital volume control can clip,
the input signal should be sufficiently attenuated. High attack rates can cause audible artifacts, and
too-slow attack rates may not be able to prevent the input signal from clipping.
The recommended DRC attack rate value is 1.9531e–4 dB per sample period.
5.5.4.5
DRC Decay Rate
When the DRC detects a reduction in output signal swing beyond the programmed DRC threshold, the
DRC enters a decay state, where the applied gain in the digital-volume control is gradually increased to
programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the decay
rate programmed through page 0 / register 70, bits D3–D0. The decay rates can be programmed from
1.5625e–3 dB per sample period to 4.7683e–7 dB per sample period. If the decay rates are programmed
too fast, then sudden gain changes can cause audible artifacts. However, if it is programmed too slow,
then the output may be perceived as too low for a long time after the peak signal has passed.
The recommended value of DRC decay rate is 2.4414e–5 dB per sample period.
34
APPLICATION INFORMATION
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3100
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