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參數(shù)資料
型號(hào)： TLV320DAC3100IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 69/97頁
文件大小： 1134K
代理商： TLV320DAC3100IRHBT
www.ti.com
SLAS671 – FEBRUARY 2010
Page 0 / Register 65 (0x41): DAC Left Volume Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
Left DAC Channel Digital Volume Control Setting
0111 1111–0011 0001: Reserved. Do not use
0011 0000: Digital volume control = 24 dB
0010 1111: Digital volume control = 23.5 dB
0010 1110: Digital volume control = 23 dB
...
0000 0001: Digital volume control = 0.5 dB
0000 0000: Digital volume control = 0 dB
1111 1111: Digital volume control = –0.5 dB
...
1000 0010: Digital volume control = –63 dB
1000 0001: Digital volume control = –63.5 dB
1000 0000: Reserved
Page 0 / Register 66 (0x42): DAC Right Volume Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
Right DAC Channel Digital Volume Control Setting
0111 1111–0011 0001: Reserved. Do not use
0011 0000: Digital volume control = 24 dB
0010 1111: Digital volume control = 23.5 dB
0010 1110: Digital volume control = 23 dB
...
0000 0001: Digital volume control = 0.5 dB
0000 0000: Digital volume control = 0 dB
1111 1111: Digital volume control = –0.5 dB
...
1000 0010: Digital volume control = –63 dB
1000 0001: Digital volume control = –63.5 dB
1000 0000: Reserved
Page 0 / Register 67 (0x43): Headset Detection
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Headset detection disabled
1: Headset detection enabled
D6–D5
R
XX
00: No headset detected
01: Headset without microphone is detected
10: Reserved
11: Headset with microphone is detected
D4–D2
R/W
000
Debounce Programming for Glitch Rejection During Headset Detection(1)
000: 16 ms (sampled with 2-ms clock)
001: 32 ms (sampled with 4-ms clock)
010: 64 ms (sampled with 8-ms clock)
011: 128 ms (sampled with 16-ms clock)
100: 256 ms (sampled with 32-ms clock)
101: 512 ms (sampled with 64-ms clock)
110: Reserved
111: Reserved
D1–D0
R/W
00
Debounce Programming for Glitch Rejection During Headset Button-Press Detection
00: 0 ms
01: 8 ms (sampled with 1-ms clock)
10: 16 ms (sampled with 2-ms clock)
11: 32 ms (sampled with 4-ms clock)
(1)
Note that these times are generated using the 1-MHz reference clock which is defined in page 3 / register 16.
Copyright 2010, Texas Instruments Incorporated
REGISTER MAP
71
Product Folder Link(s): TLV320DAC3100
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TLV320DAC3120 制造商:TI 制造商全稱:Texas Instruments 功能描述:
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