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參數(shù)資料
型號： TLV320DAC3100IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 71/97頁
文件大小： 1134K
代理商： TLV320DAC3100IRHBT
www.ti.com
SLAS671 – FEBRUARY 2010
Page 0 / Register 71 (0x47): Left Beep Generator (1)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Beep generator is disabled.
1: Beep generator is enabled (self-clearing based on beep duration).
D6
R/W
0
Reserved. Write only reset value.
D5–D0
R/W
00 0000
00 0000: Left-channel beep volume control = 2 dB
00 0001: Left-channel beep volume control = 1 dB
00 0010: Left-channel beep volume control = 0 dB
00 0011: Left-channel beep volume control = –1 dB
...
11 1110: Left-channel beep volume control = –60 dB
11 1111: Left-channel beep volume control = –61 dB
(1)
The beep generator is only available in PRB_P25 DAC processing mode.
Page 0 / Register 72 (0x48): Right Beep Generator(1)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
00: Left and right channels have independent beep volume control.
01: Left-channel beep volume control is the programmed value of right-channel beep volume control.
10: Right-channel beep volume control is the programmed value of left-channel beep volume control.
11: Same as 00
D5–D0
R/W
00 0000
00 0000: Right-channel beep volume control = 2 dB
00 0001: Right-channel beep volume control = 1 dB
00 0010: Right-channel beep volume control = 0 dB
00 0011: Right-channel beep volume control = –1 dB
...
11 1110: Right-channel beep volume control = –60 dB
11 1111: Right-channel beep volume control = –61 dB
(1)
The beep generator is only available in PRB_P25 DAC processing mode.
Page 0 / Register 73 (0x49): Beep Length MSB
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
8 MSBs out of 24 bits for the number of samples for which the beep must be generated.
Page 0 / Register 74 (0x4A): Beep Length Middle Bits
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
8 middle bits out of 24 bits for the number of samples for which the beep must be generated.
Page 0 / Register 75 (0x4B): Beep Length LSB
＝
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
1110 1110
8 LSBs out of 24 bits for the number of samples for which beep need to be generated.
Page 0 / Register 76 (0x4C): Beep Sin(x) MSB
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0001 0000
8 MSBs out of 16 bits for sin(2p × fin/fS), where fin is the beep frequency and fS is the DAC sample rate.
Page 0 / Register 77 (0x4D): Beep Sin(x) LSB
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
1101 1000
8 LSBs out of 16 bits for sin(2p × fin/fS), where fin is the beep frequency and fS is the DAC sample rate.
Copyright 2010, Texas Instruments Incorporated
REGISTER MAP
73
Product Folder Link(s): TLV320DAC3100
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