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參數(shù)資料
型號(hào)： TLV320DAC3100IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 77/97頁
文件大小： 1134K
代理商： TLV320DAC3100IRHBT
www.ti.com
SLAS671 – FEBRUARY 2010
Page 1 / Register 44 (0x2C): HP Driver Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
Debounce Time for Headset Short-Circuit Detection
MCLK/DIV (Page 3 /
(1)
register 16) = 1-MHz
Internal Oscillator Source
Source
000: Debounce time =
0 ms
001: Debounce time =
8 ms
7.8 ms
010: Debounce time =
16 ms
15.6 ms
011: Debounce time =
32 ms
31.2 ms
100: Debounce time =
64 ms
62.4 ms
101: Debounce time =
128 ms
124.9 ms
110: Debounce time =
256 ms
250 ms
111: Debounce time =
512 ms
500 ms
Note: These values are based on a nominal oscillator
frequency of 8.2 MHz. The values scale according to
the actual oscillator frequency.
D4–D3
R/W
00
00: Default mode for the DAC
01: DAC performance increased by increasing the current
10: Reserved
11: DAC performance increased further by increasing the current again
D2
R/W
0
0: HPL output driver is programmed as headphone driver.
1: HPL output driver is programmed as lineout driver.
D1
R/W
0
0: HPR output driver is programmed as headphone driver.
1: HPR output driver is programmed as lineout driver.
D0
R/W
0
Reserved. Write only zero to this bit.
(1)
The clock used for the debounce has a clock period = debounce duration/8.
Page 1 / Register 45 (0x2D): Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Do not write to this register.
Page 1 / Register 46 (0x2E): MICBIAS
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Device software power down is not enabled.
1: Device software power down is enabled.
D6–D4
R/W
000
Reserved. Write only zeros to these bits.
D3
R/W
0
0: Programmed MICBIAS is not powered up if headset detection is enabled but headset is not inserted.
1: Programmed MICBIAS is powered up even if headset is not inserted.
D2
R/W
0
Reserved. Write only zero to this bit.
D1–D0
R/W
00
00: MICBIAS output is powered down.
01: MICBIAS output is powered to 2 V.
10: MICBIAS output is powered to 2.5 V.
11: MICBIAS output is powered to AVDD.
Page 1 / Register 47 (0x2F) Through Page 1 / Register 49 (0x31): Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R
XXXX XXXX
Reserved. Do not write to these bits.
Page 1 / Register 50 (0x32): Input CM Settings
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: AIN1 input is floating if it is not used for analog bypass.
1: AIN1 input is connected to CM internally if it is not used for analog bypass.
D6
R/W
0
0: AIN2 input is floating if it is not used for analog bypass.
1: AIN2 input is connected to CM internally if it is not used for analog bypass.
D5–D0
R/W
00 0000
Reserved. Write only zeros to these bits.
Copyright 2010, Texas Instruments Incorporated
REGISTER MAP
79
Product Folder Link(s): TLV320DAC3100
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