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參數(shù)資料
型號(hào)： TLV320DAC3100IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 40/97頁(yè)
文件大小： 1134K
代理商： TLV320DAC3100IRHBT
www.ti.com
SLAS671 – FEBRUARY 2010
In all cases, DOSR is limited in its range by the following condition:
2.8 MHz < DOSR × DAC_fS < 6.2 MHz
Based on the identified filter type and the required signal-processing capabilities, the appropriate
processing block can be determined from the list of available processing blocks (PRB_P1 to PRB_P25).
Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock-divider
values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of
flexibility.
In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL)
divided by MDAC, NDAC, and DOSR must be equal to the DAC sampling rate, DAC_fS. The
CODEC_CLKIN clock signal is shared with the DAC clock-generation block.
CODEC_CLKIN = NDAC × MDAC × DOSR × DAC_fS
To a large degree, NDAC and MDAC can be chosen independently in the range of 1 to 128. In general,
NDAC should be as large as possible as long as the following condition can still be met:
MDAC × DOSR / 32
≥ RC
RC is a function of the chosen processing block and is listed in Table 5-11.
The common-mode voltage setting of the device is determined by the available analog power supply.
At this point, the following device-specific parameters are known: PRB_Rx, DOSR, NDAC, MDAC, input
and output common-mode values. If the PLL is used, the PLL parameters P, J, D, and R are determined
as well.
Step 2
Setting up the device via register programming:
The following list gives an example sequence of items that must be executed in the time between
powering the device up and reading data from the device. Note that there are other valid sequences,
depending on which features are used.
1. Define starting point:
(a) Power up applicable external power supplies
(b) Set register page to 0
(c) Initiate SW reset
2. Program clock settings
(a) Program PLL clock dividers P, J, D, and R (if PLL is used)
(b) Power up PLL (if PLL is used)
(c) Program and power up NDAC
(d) Program and power up MDAC
(e) Program OSR value
(f) Program I2S word length if required (16, 20, 24, or 32 bits)
(g) Program the processing block to be used
(h) Micellaneous page 0 controls
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
45
Product Folder Link(s): TLV320DAC3100
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