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參數資料
| 型號： | TLV320DAC3100IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數： | 53/97頁 |
| 文件大小： | 1134K |
| 代理商： | TLV320DAC3100IRHBT |
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LD(n)
LD (n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
0
3
2
1
N
-
1
N
-
2
N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
www.ti.com
SLAS671 – FEBRUARY 2010
Figure 5-32. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For the DSP mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
5.7.2
Primary and Secondary Digital Audio Interface Selection
The audio serial interface on the TLV320DAC3100 has extensive I/O control to allow communication with
two independent processors for audio data. The processors can communicate with the device one at a
time. This feature is enabled by register programming of the various pin selections. Table 5-30 shows the
primary and secondary audio interface selection and registers. Figure 5-33 is a high-level diagram
showing the general signal flow and multiplexing for the primary and secondary audio interfaces.
Table 5-30. Primary and Secondary Audio Interface Selection
Desired Pin
Possible
Page 0 Registers
Comment
Function
Pins
R27/D2 = 1
Primary WCLK is output from codec
Primary WCLK
WCLK
(OUT)
R33/D5–D4
Select source of primary WCLK (DAC_fs or secondary WCLK)
Primary WCLK (IN)
WCLK
R27/D2 = 0
Primary WCLK is input to codec
R27/D3 = 1
Primary BCLK is output from codec
Primary BCLK
BCLK
(OUT)
R33/D7
Select source of primary WCLK (internal BCLK or secondary BCLK)
Primary BCLK (IN)
BCLK
R27/D3 = 0
Primary BCLK is input to codec
Primary DIN (IN)
DIN
R32/D0
Select DIN to internal interface (0 = primary DIN; 1 = secondary DIN)
R31/D4–D2 = 000
Secondary WCLK obtained from GPIO1 pin
Secondary WCLK
GPIO1
R51/D5–D2 = 1001
GPIO1 = secondary WCLK output
(OUT)
R33/D3–D2
Select source of secondary WCLK (DAC_fs, or primary WCLK)
R31/D4–D2 = 000
Secondary WCLK obtained from GPIO1 pin
Secondary WCLK
GPIO1
(IN)
R51/D5–D2 = 0001
GPIO1 enabled as secondary input
R31/D7–D5 = 000
Secondary BCLK obtained from GPIO1 pin
Secondary BCLK
GPIO1
R51/D5–D2 = 1000
GPIO1 = secondary BCLK output
(OUT)
R33/D6
Select source of secondary BCLK (primary BCLK or internal BCLK)
R31/D7–D5 = 000
Secondary BCLK obtained from GPIO1 pin
Secondary BCLK
GPIO1
(IN)
R51/D5–D2 = 0001
GPIO1 enabled as secondary input
R31/D1–D0 = 00
Secondary DIN obtained from GPIO1 pin
Secondary DIN (IN)
GPIO1
R51/D5–D2 = 0001
GPIO1 enabled as secondary input
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
57
Product Folder Link(s): TLV320DAC3100
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