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參數(shù)資料
| 型號： | TLV320DAC3100IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 43/97頁 |
| 文件大小： | 1134K |
| 代理商： | TLV320DAC3100IRHBT |
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SLAS671 – FEBRUARY 2010
www.ti.com
w 30 3F D4
#
# DAC Left gain = -22 dB
w 30 41 D4
# DAC Right gain = -22 dB
w 30 42 D4
#
(c) Unmute digital volume control
#
# Unmute DAC left and right channels
w 30 40 00
5.6
CLOCK Generation and PLL
The TLV320DAC3100 supports a wide range of options for generating clocks for the DAC section as well
as interface and other control blocks, as shown in Figure 5-20. The clocks for the DAC require a source
reference clock. This clock can be provided on variety of device pins, such as the MCLK, BCLK, or GPIO1
pins. The source reference clock for the codec can be chosen by programming the CODEC_CLKIN value
on page 0 / register 4, bits D1–D0. CODEC_CLKIN can then be routed through highly-flexible clock
dividers, shown in Figure 5-20, to generate the various clocks required for the DAC. In the event that the
desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO1, the
TLV320DAC3100 also provides the option of using the on-chip PLL, which supports a wide range of
fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the
TLV320DAC3100 provides several programmable clock dividers to help achieve a variety of sampling
rates for the DAC.
48
APPLICATION INFORMATION
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3100
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| TLV320DAC3101IRHBT | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Low-Pwr audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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