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參數資料
| 型號： | TLV320DAC3100IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數： | 74/97頁 |
| 文件大小： | 1134K |
| 代理商： | TLV320DAC3100IRHBT |
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SLAS671 – FEBRUARY 2010
www.ti.com
Page 1 / Register 32 (0x20): Class-D Speaker Amplifier
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Class-D output driver is powered down.
1: Class-D output driver is powered up.
D6–D1
R/W
000 011
Reserved. Write only the reset value to these bits.
D0
R
0
0: Short circuit is not detected on the class-D driver. Valid only if class-D amplifier is powered up. For
short-circuit flag sticky bit, see page 0 / register 44.
1: Short circuit is detected on the class-D driver. Valid only if class-D amplifier is powered up. For short-
circuit flag sticky bit, see page 0 / register 44.
Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: If power-down sequence is activated by device software, power down using page 1 / register 46,
bit D7, then power down the DAC simultaneously with the HP and SP amplifiers.
1: If power-down sequence is activated by device software, power down using page 1 / register 46,
bit D7, then power down DAC only after HP and SP amplifiers are completely powered down. This is
to minimize power-down POP.
D6–D3
R/W
0111
0000: Driver power-on time = 0 ms
0001: Driver power-on time = 15.3 ms
0010: Driver power-on time = 153 ms
0011: Driver power-on time = 1.53 ms
0100: Driver power-on time = 15.3 ms
0101: Driver power-on time = 76.2 ms
0110: Driver power-on time = 153 ms
0111: Driver power-on time = 304 ms
1000: Driver power-on time = 610 ms
1001: Driver power-on time = 1.22 s
1010: Driver power-on time = 3.04 s
1011: Driver power-on time = 6.1 s
1100–1111: Reserved. Do not write these sequences to these bits.
NOTE: These values are based on typical oscillator frequency of 8.2 MHz. The values scale according
to the actual oscillator frequency.
D2–D1
R/W
11
00: Driver ramp-up step time = 0 ms
01: Driver ramp-up step time = 0.98 ms
10: Driver ramp-up step time = 1.95 ms
11: Driver ramp-up step time = 3.9 ms
NOTE: These values are based on typical oscillator frequency of 8.2 MHz. The values scale according
to the actual oscillator frequency.
D0
R/W
0
0: Weakly driven output common-mode voltage is generated from resistor divider of the AVDD supply.
1: Weakly driven output common-mode voltage is generated from band-gap reference.
Page 1 / Register 34 (0x22): Output Driver PGA Ramp-Down Period Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Reserved. Write only the reset value to this bit.
D6–D4
R/W
000
Speaker Power-Up Wait Time (Duration Based on Using Internal Oscillator)
000: Wait time = 0 ms
001: Wait time = 3.04 ms
010: Wait time = 7.62 ms
011: Wait time = 12.2 ms
100: Wait time = 15.3 ms
101: Wait time = 19.8 ms
110: Wait time = 24.4 ms
111: Wait time = 30.5 ms
NOTE: These values are based on typical oscillator frequency of 8.2 MHz. The values scale according
to the actual oscillator frequency.
D3–D0
R/W
0000
Reserved. Write only the reset value to these bits.
76
REGISTER MAP
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3100
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