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參數資料
| 型號： | AD9874 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, TQFP-48 |
| 文件頁數： | 16/40頁 |
| 文件大小： | 744K |
| 代理商： | AD9874 |
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REV. 0
–16–
AD9874
FS
DOUT
CLKOUT
SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0
I15
I0
Q15
Q14
Q0
CLKOUT
FS
DOUT
SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC = 0
I15
I0
Q15
Q14
Q0
RSSI0
ATTEN6
ATTN7
CLKOUT
FS
DOUT
SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0
I15
I0
Q15
Q14
Q0
CLKOUT
FS
DOUT
SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0
SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0: AS ABOVE, BUT FS IS LOW
IDLE (HIGH) BITS
START
BIT
START
BIT
STOP
BIT
STOP
BIT
START
BIT
HI-Z
I15
I8
I7
I0
Q15
Figure 3a. SSI Timing for Several SSICRA Settings with 16-Bit I/Q Data
Table IV. Number of Bits per Frame for Different
SSICR Settings
Number of Bits
per Frame
DW
EAGC
EFS
AAGC
0 (16-bit)
0
0
1
1
1
1
0
1
0
0
1
1
NA
NA
0
1
0
1
32
49
*
48
40
69
*
59
*
1 (24-bit)
0
0
1
1
1
1
0
1
0
0
1
1
NA
NA
0
1
0
1
48
69
*
64
56
89
*
79
*
*
The number of bits per frame with embedded frame sync (EFS = 1) assume at
least 10 idle bits are desired.
The
maximum
SSIORD setting can be determined by the
following equation:
SSIORD
where
TRUNC
is the truncated integer value.
Table IV lists the number of bits within a frame for 16-bit and
24-bit output data formats for all of the different SSICR settings.
The decimation factor is determined by the contents of
Register 0x07.
TRUNC Dec Factor
{(
of Bits per Frame
≤
.
)/(#
)}
(1)
An example helps illustrate how the maximum SSIORD setting
is determined. Suppose a user selects a decimation factor of 600
(Register 0x07, K = 0, M = 9) and prefers a 3-wire interface
with a dedicated frame sync (EFS = 0) containing 24-bit data
(DW = 1) with nonalternating embedded AGC data included
(EAGC = 1, AAGC = 0). Referring to Table IV, each frame will
consist of 64 data bits. Using Equation 1, the maximum
SSIORD setting is 9 (=
TRUNC
(600/64)). Thus, the user can
select any SSIORD setting between 1 and 9.
Figure 3a illustrates the output timing of the SSI port for several
SSI control register settings with 16-bit I/Q data, while Figure 3b
shows the associated timing parameters. Note, the same timing
relationship holds for 24-bit I/Q data, with the exception that I and
Q word lengths now become 24 bits. In the default mode of the
operation, data is shifted out on rising edges of CLKOUT after a
pulse equal to a clock period is output from the Frame Sync (FS)
Pin. As described above, the output data consists of a 16- or 24-bit
I sample followed by a 16- or 24-bit Q sample, plus two optional
bytes containing AGC and status information.
FS
DOUT
I15
I14
CLKOUT
t
V
t
CLK
t
HI
t
LOW
t
DV
Figure 3b. Timing Parameters for SSI Timing*
*
Timing parameters also apply to inverted CLKOUT or FS modes with t
DV
relative to the falling edge of the CLK and/or FS.
相關PDF資料 |
PDF描述 |
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| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
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