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參數資料
型號： AD9874
廠商： ANALOG DEVICES INC
元件分類： 通信及網絡
英文描述： IF Digitizing Subsystem
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP48
封裝： 1.40 MM HEIGHT, PLASTIC, TQFP-48
文件頁數： 3/40頁
文件大?。?/td> 744K
代理商： AD9874
REV. 0
–3–
AD9874
DIGITAL SPECIFICATIONS
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD= VDDH= 2.7 to 3.6 V, VDDQ= VDDP = 2.7 V to 5.5 V,
f
CLK
= 18 MSPS, f
IF
= 109.65 MHz, f
LO
= 107.4 MHz, f
REF
= 16.8 MHz, unless otherwse noted.)
1
Parameter
T emp
T est Level
Min
T yp
Max
Unit
DECIMAT OR
Decimation Factor
2
Pass-Band Width
Pass-Band Gain Variation
Alias Attenuation
Full
Full
Full
Full
IV
V
IV
IV
48
960
50%
f
CLK OUT
dB
dB
1.2
88
SPI-READ OPERAT ION (See Figure 1a)
PC Clock Frequency
PC Clock Period (t
CLK
)
PC Clock HI (t
HI
)
PC Clock LOW (t
LOW
)
PC to PD Setup T ime (t
DS
)
PC to PD Hold T ime (t
DH
)
PE
to PC Setup T ime (t
S
)
PC to
PE
Hold T ime (t
H
)
SPI-WRIT E OPERAT ION
3
(See Figure 1b)
PC Clock Frequency
PC Clock Period (t
CLK
)
PC Clock HI (t
HI
)
PC Clock LOW (t
LOW
)
PC to PD Setup T ime (t
DS
)
PC to PD Hold T ime (t
DH
)
PC to PD (or DOUBT ) Data Valid T ime (t
DV
)
PE
to PD Output Valid to Hi-Z (t
EZ
)
SSI
3
(see Figure 2b)
CLK OUT Frequency
CLK OUT Period (t
CLK
)
CLK OUT Duty Cycle (t
HI,
t
LOW
)
CLK OUT to FS Valid T ime (t
)
CLK OUT to DOUT Data Valid T ime (t
DV
)
CMOS LOGIC INPUT S
4
Logic “1” Voltage (V
IH
)
Logic “0” Voltage (V
IL
)
Logic “1” Current (V
IH
)
Logic “0” Current (V
IL
)
Input Capacitance
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
10
MHz
ns
ns
ns
ns
ns
ns
ns
100
45
45
2
2
5
5
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
10
MHz
ns
ns
ns
ns
ns
ns
ns
100
45
45
2
2
3
8
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
0.867
38.4
33
–1
–1
26
1153
67
1
1
MHz
ns
ns
ns
ns
50
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
VDDH–0.2
V
V
m
A
m
A
pF
0.5
10
10
3
CMOS LOGIC OUT PUT S
3,4,5
Logic “1” Voltage (V
IH
)
Logic “0” Voltage (V
IL
)
Full
Full
IV
IV
VDDH–0.2
V
V
0.2
NOT ES
1
Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f
CLK
= 18 MHz, decimation factor = 300, 10 pF load on SSI output pins:
VDDx = 3.0 V.
2
Programmable in steps of 48 or 60.
3
CMOS output mode with C
= 10 pF and Drive Strength = 7.
4
Absolute Max and Min input/output levels are VDDH +0.3 V and –0.3 V.
5
I
OL
= 1 mA; specification is also dependent on Drive Strength setting.
Specifications subject to change without notice.
相關PDF資料
PDF描述
AD9874BST IF Digitizing Subsystem
AD9874EB IF Digitizing Subsystem
AD9875BSTRL Broadband Modem Mixed-Signal Front End
AD9875 Broadband Modem Mixed-Signal Front End
AD9875-EB Broadband Modem Mixed-Signal Front End
相關代理商/技術參數
參數描述
AD9874ABST 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:*
AD9874ABST 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48
AD9874ABST 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM
AD9874ABSTRL 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:*
AD9874ABSTZ 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem
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