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參數資料
| 型號： | AD9874 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, TQFP-48 |
| 文件頁數： | 19/40頁 |
| 文件大小： | 744K |
| 代理商： | AD9874 |
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REV. 0
AD9874
–19–
An example may help illustrate how the values of
LOA
,
LOB
, and
LOR
can be selected. Consider an application employing a 13 MHz
crystal oscillator (i.e., f
REF
= 13 MHz) with the requirement that
f
REF
= 100 kHz and
f
LO
= 143 MHz (i.e., high side injection with
f
IF
= 140.75 MHz and
f
CLK
= 18 MSPS). LOR is selected to be
130 such that f
REF
= 100 kHz. The N-divider factor is 1430,
which can be realized by selecting LOB = 178 and LOA = 6.
The stability, phase noise, spur performance, and transient
response of the AD9874
’
s LO (and CLK) synthesizers are deter-
mined by the external loop filter, the VCO, the N-divide factor,
and the reference frequency, FREF. A good overview of the
theory and practical implementation of PLL synthesizers (fea-
tured as a three-part series in
Analog Dialogue
) can be found at:
www.analog.com/library/analogDialogue/archives/33-03/phase/www.analog.com/library/analogDialogue/archives/33-05/
phase_locked/index.html
www.analog.com/library/analogDialogue/archives/33-07/
phase3/index.html
Also, a free software copy of the Analog Devices ADIsimPLL,
a PLL synthesizer simulation tool, is available at
www.analog.com/
technology/RFComms/rfif/ADIsimPLL.html
. Note, the ADF4112
model can be used as a close approximation to the AD9874
’
s
LO synthesizer when using this software tool.
FREF
84k
~VDDL/2
LO
BUFFER
500
500
TO MIXER
LO PORT
1.75V
BIAS
LOP
LON
NOTES
1. ESD DIODE STRUCTURES OMITTED FOR CLARITY.
2. FREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON.
Figure 6. Equivalent Input of LO and REF Buffers
Figure 6 shows the equivalent input structures of the synthesiz-
ers
’
LO and REF buffers (excluding the ESD structures). The
LO input is fed to the LO synthesizer
’
s buffer as well as the
AD9874
’
s mixer
’
s LO port. Both inputs are self-biasing and
thus tolerate ac-coupled inputs. The LO input can be driven
with a single-ended or differential signal. Single-ended dc-
coupled inputs should ensure sufficient signal swing above and
below the common-mode bias of the LO and REF buffers
(i.e., 1.75 V and VDDL/2). Note, the FREF input is slew rate
dependent and must be driven with input signals exceeding
6.4 V/
m
sec to ensure synthesizer operation.
Fast Acquire Mode
The fast acquire circuit attempts to boost the output current when
the phase difference between the divided-down LO (i.e., f
LO
)
and the divided-down reference frequency (i.e., f
REF
) exceeds the
threshold determined by the LOFA Register. The LOFA Register
specifies a divisor for the f
REF
signal that determines the period
(T) of this divided-down clock. This period defines the time
interval used in the fast acquire algorithm to control the charge
pump current.
Assume for the moment that the nominal charge pump current
is at its lowest setting (i.e., LOI = 0) and denote this minimum
current by I
0
. When the output pulse from the phase comparator
exceeds T, the output current for the next pulse is 2 I
0
. When
the pulse is wider than 2 T, the output current for the next pulse is
3 I
0
, and so forth, up to eight times the minimum output current.
If the nominal charge pump current is more than the minimum
value (i.e., LOI > 0), the preceding rule is only applied if it results
in an increase in the instantaneous charge pump current. If the
charge pump current is set to its lowest value (LOI = 0) and the
fast acquire circuit is enabled, the instantaneous charge pump
current will never fall below 2 I
0
when the pulsewidth is less than
T. Thus, the charge pump current when fast acquire is enabled
is given by:
I
The recommended setting for LOFA is LOR/16. Choosing a larger
value for LOFA will increase
T
. Thus, for a given phase differ-
ence between the LO input and the f
REF
input, the instantaneous
charge pump current will be less than that available for a LOFA
value of LOR/16. Similarly, a smaller value for LOFA will decrease
T
, making more current available for the same phase difference.
In other words, a smaller value of LOFA will enable the synthe-
sizer to settle faster in response to a frequency hop than will a
large LOFA value. Care must be taken to choose a value for
LOFA that is large enough (values greater than 4 recommended)
to prevent the loop from oscillating back and forth in response
to a frequency hop.
I
LOI,
PUMP FA
=
￥
+
0
1
1
{
max( ,
_
)}
(4)
T able VII. SPI Registers Associated with LO Synthesizer
Address
(Hex)
0x00
0x08
0x09
0x0A
Bit
Breakdown
(7:0)
(5:0)
(7:0)
(7:5)
(4:0)
(7:0)
(6)
(5)
(4:2)
(1:0)
(3:0)
(7:0)
Default
Value
0xFF
0x00
0x38
0x5
0x00
0x1D
0
0
0
0
0x0
0x04
Width
1
6
8
3
5
8
1
1
3
2
4
8
Name
STBY
LOR(13:8)
LOR(7:0)
LOA
LOB(12:8)
LOB(7:0)
LOF
LOINV
LOI
LOTM
LOFA(13:8)
LOFA(7:0)
0x0B
0x0C
0x0D
0x0E
相關PDF資料 |
PDF描述 |
|---|---|
| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
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